AxisToJtag Entity Reference

Inheritance diagram for AxisToJtag:

Collaboration diagram for AxisToJtag:

Entities
AxisToJtag.AxisToJtagImpl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
numeric_std
StdRtlPkg	Package <StdRtlPkg>
AxiStreamPkg	Package <AxiStreamPkg>
AxisToJtagPkg	Package <AxisToJtagPkg>

Generics
TPD_G	time := 1 ns
AXIS_FREQ_G	real := 0 . 0
AXIS_WIDTH_G	positive range 4 to 16 := 4
CLK_DIV2_G	positive := 4
MEM_DEPTH_G	natural range 0 to 65535 := 4
MEM_STYLE_G	string := " auto "

Ports
axisClk	in	sl
axisRst	in	sl
mAxisReq	in	AxiStreamMasterType
sAxisReq	out	AxiStreamSlaveType
mAxisTdo	out	AxiStreamMasterType
sAxisTdo	in	AxiStreamSlaveType
tck	out	sl
tdi	out	sl
tms	out	sl
tdo	in	sl

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The documentation for this design unit was generated from the following file:

• xilinx/xvc-udp/jtag/rtl/AxisToJtag.vhd