AxiXcf128Reg Entity Reference

Inheritance diagram for AxiXcf128Reg:

Entities
AxiXcf128Reg.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_unsigned
std_logic_arith
StdRtlPkg	Package <StdRtlPkg>
AxiLitePkg	Package <AxiLitePkg>
AxiXcf128Pkg	Package <AxiXcf128Pkg>

Generics
TPD_G	time := 1 ns
AXI_CLK_FREQ_G	real := 200 . 0E + 6

Ports
axiReadMaster	in	AxiLiteReadMasterType
axiReadSlave	out	AxiLiteReadSlaveType
axiWriteMaster	in	AxiLiteWriteMasterType
axiWriteSlave	out	AxiLiteWriteSlaveType
status	in	AxiXcf128StatusType
config	out	AxiXcf128ConfigType
axiClk	in	sl
axiRst	in	sl

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The documentation for this design unit was generated from the following file:

• devices/Xilinx/xcf128/rtl/AxiXcf128Reg.vhd