AxiXcf128Reg.rtl Architecture Reference

Architecture >> AxiXcf128Reg::rtl

Processes
comb	( axiReadMaster , axiRst , axiWriteMaster , r , status )
seq	( axiClk )

Constants
MAX_CNT_C	natural := ( getTimeRatio ( AXI_CLK_FREQ_G , 10 . 0E + 6 ) ) - 1
REG_INIT_C	RegType := ( ( others = > ' 0 ' ) , ( others = > ( others = > ' 0 ' ) ) , ' 0 ' , 0 , AXI_XCF128_CONFIG_INIT_C , IDLE_S , AXI_LITE_READ_SLAVE_INIT_C , AXI_LITE_WRITE_SLAVE_INIT_C )

Types
StateType	( IDLE_S , CMD_LOW_S , CMD_HIGH_S , WAIT_S , DATA_LOW_S , DATA_HIGH_S )

Signals
r	RegType := REG_INIT_C
rin	RegType

Records
RegType

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The documentation for this design unit was generated from the following file:

• devices/Xilinx/xcf128/rtl/AxiXcf128Reg.vhd