AxiXadcMinimumCore Entity Reference

Entities
AxiXadcMinimumCore.mapping	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
StdRtlPkg	Package <StdRtlPkg>
AxiLitePkg	Package <AxiLitePkg>

Generics
TPD_G	time := 1 ns

Ports
vPIn	in	sl
vNIn	in	sl
axiReadMaster	in	AxiLiteReadMasterType
axiReadSlave	out	AxiLiteReadSlaveType
axiWriteMaster	in	AxiLiteWriteMasterType
axiWriteSlave	out	AxiLiteWriteSlaveType
axiClk	in	sl
axiRst	in	sl

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The documentation for this design unit was generated from the following file:

• xilinx/7Series/xadc/rtl/AxiXadcMinimumCore.vhd