AxiXadcMinimumCore.mapping Architecture Reference

Architecture >> AxiXadcMinimumCore::mapping

Components
AxiXadcMinimum

Signals
axiRstL	sl

Attributes
SYN_BLACK_BOX	boolean
SYN_BLACK_BOX	component is true
BLACK_BOX_PAD_PIN	string
BLACK_BOX_PAD_PIN	component is " s_axi_aclk , s_axi_aresetn , s_axi_awaddr [ 10 : 0 ] , s_axi_awvalid , s_axi_awready , s_axi_wdata [ 31 : 0 ] , s_axi_wstrb [ 3 : 0 ] , s_axi_wvalid , s_axi_wready , s_axi_bresp [ 1 : 0 ] , s_axi_bvalid , s_axi_bready , s_axi_araddr [ 10 : 0 ] , s_axi_arvalid , s_axi_arready , s_axi_rdata [ 31 : 0 ] , s_axi_rresp [ 1 : 0 ] , s_axi_rvalid , s_axi_rready , ip2intc_irpt , vp_in , vn_in , channel_out [ 4 : 0 ] , eoc_out , alarm_out , eos_out , busy_out "

Instantiations
axixadccore_1	axixadcminimum

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The documentation for this design unit was generated from the following file:

• xilinx/7Series/xadc/rtl/AxiXadcMinimumCore.vhd