AxiWriteEmulate.structure Architecture Reference

Architecture >> AxiWriteEmulate::structure

Processes
comb	( axiRst , intWriteMaster , r )
seq	( axiClk )
comb	( axiRst , intWriteMaster , r )
seq	( axiClk )

Constants
REG_INIT_C	RegType := ( latency = > 0 , cnt = > ( others = > ' 0 ' ) , state = > IDLE_S , iMaster = > AXI_WRITE_MASTER_INIT_C , iSlave = > AXI_WRITE_SLAVE_INIT_C )

Types
StateType	( IDLE_S , DATA_S , WAIT_S , RESP_S )

Signals
r	RegType := REG_INIT_C
rin	RegType
intWriteMaster	AxiWriteMasterType
intWriteSlave	AxiWriteSlaveType

Records
RegType

Instantiations
u_axiwritepathfifo	AxiWritePathFifo <Entity AxiWritePathFifo>
u_axiwritepathfifo	AxiWritePathFifo <Entity AxiWritePathFifo>

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The documentation for this design unit was generated from the following files:

• axi/axi4/rtl/AxiWriteEmulate.vhd
• build/SRC_VHDL/surf/AxiWriteEmulate.vhd