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AxiToAxiLite Entity Reference
Inheritance diagram for AxiToAxiLite:Entities | |
| AxiToAxiLite.mapping | architecture |
Libraries | |
| ieee | |
| surf | |
Use Clauses | |
| std_logic_1164 | |
| std_logic_unsigned | |
| std_logic_arith | |
| StdRtlPkg | Package <StdRtlPkg> |
| AxiLitePkg | Package <AxiLitePkg> |
| AxiPkg | Package <AxiPkg> |
Generics | |
| TPD_G | time := 1 ns |
| EN_SLAVE_RESP_G | boolean := true |
Ports | ||
| axiClk | in | sl |
| axiClkRst | in | sl |
| axiReadMaster | in | AxiReadMasterType |
| axiReadSlave | out | AxiReadSlaveType |
| axiWriteMaster | in | AxiWriteMasterType |
| axiWriteSlave | out | AxiWriteSlaveType |
| axilReadMaster | out | AxiLiteReadMasterType |
| axilReadSlave | in | AxiLiteReadSlaveType |
| axilWriteMaster | out | AxiLiteWriteMasterType |
| axilWriteSlave | in | AxiLiteWriteSlaveType |
The documentation for this design unit was generated from the following files:
- axi/bridge/rtl/AxiToAxiLite.vhd
- build/SRC_VHDL/surf/AxiToAxiLite.vhd
