AxiToAxiLite.mapping Architecture Reference

Architecture >> AxiToAxiLite::mapping

Processes
PROCESS_20	( axiWriteMaster )
PROCESS_21	( axilReadSlave )
PROCESS_22	( axiClk )
PROCESS_95	( axiWriteMaster )
PROCESS_96	( axilReadSlave )
PROCESS_97	( axiClk )

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The documentation for this design unit was generated from the following files:

• axi/bridge/rtl/AxiToAxiLite.vhd
• build/SRC_VHDL/surf/AxiToAxiLite.vhd