AxiStreamTrailerAppend.rtl Architecture Reference

Architecture >> AxiStreamTrailerAppend::rtl

Processes
comb	( axisRst , pipeAxisSlave , r , sAxisMaster , sAxisTrailerMaster )
seq	( axisClk , axisRst )
comb	( axisRst , pipeAxisSlave , r , sAxisMaster , sAxisTrailerMaster )
seq	( axisClk , axisRst )

Constants
REG_INIT_C	RegType := ( obMaster = > axiStreamMasterInit ( MASTER_SLAVE_AXI_CONFIG_G ) , ibSlaves = > ( others = > AXI_STREAM_SLAVE_INIT_C ) , sel = > ' 0 ' )

Signals
r	RegType := REG_INIT_C
rin	RegType
pipeAxisMaster	AxiStreamMasterType
pipeAxisSlave	AxiStreamSlaveType

Records
RegType

Instantiations
axistreampipeline_1	AxiStreamPipeline <Entity AxiStreamPipeline>
axistreampipeline_1	AxiStreamPipeline <Entity AxiStreamPipeline>

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The documentation for this design unit was generated from the following files:

• axi/axi-stream/rtl/AxiStreamTrailerAppend.vhd
• build/SRC_VHDL/surf/AxiStreamTrailerAppend.vhd