AxiStreamTimer.rtl Architecture Reference

Architecture >> AxiStreamTimer::rtl

Processes
comb	( axilReadIntMaster , axilWriteIntMaster , axisRst , r , streamMasters , streamSlaves )
seq	( axisClk )

Procedures
	monitorChannel( timer: slv ( 31 downto 0 ) axisMaster: in AxiStreamMasterType axisSlave: in AxiStreamSlaveType channel: in ChannelStateType variable vchannel: inout ChannelStateType variable notDoneSof: inout sl variable notDoneEof: inout sl )

Constants
CHANNEL_STATE_INIT_C	ChannelStateType := ( timeSof = > ( others = > ( others = > ' 0 ' ) ) , timeEof = > ( others = > ( others = > ' 0 ' ) ) , sofIdx = > 0 , eofIdx = > 0 , wasEof = > ' 1 ' )
REG_INIT_C	RegType := ( timer = > ( others = > ' 0 ' ) , state = > IDLE_S , channels = > ( others = > CHANNEL_STATE_INIT_C ) , axilReadSlave = > AXI_LITE_READ_SLAVE_INIT_C , axilWriteSlave = > AXI_LITE_WRITE_SLAVE_INIT_C , runCmd = > ' 0 ' )

Types
StateType	( IDLE_S , RUNNING_S , DONE_S )
ChannelStateArray	array ( natural range <> ) of ChannelStateType

Signals
axilReadIntMaster	AxiLiteReadMasterType
axilReadIntSlave	AxiLiteReadSlaveType
axilWriteIntMaster	AxiLiteWriteMasterType
axilWriteIntSlave	AxiLiteWriteSlaveType
r	RegType := REG_INIT_C
rin	RegType

Records
ChannelStateType
RegType

Instantiations
u_axil_cdc	AxiLiteAsync <Entity AxiLiteAsync>

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The documentation for this design unit was generated from the following file:

• axi/axi-stream/rtl/AxiStreamTimer.vhd