AxiStreamRingBufferTb.testbed Architecture Reference

Architecture >> AxiStreamRingBufferTb::testbed

Processes
comb	( r , rst )
seq	( clk )
comb	( r , rst )
seq	( clk )

Constants
CLK_PERIOD_C	time := 10 ns
TPD_C	time := CLK_PERIOD_C/ 4
AXIS_CONFIG_C	AxiStreamConfigType := ssiAxiStreamConfig ( dataBytes = > 2 )
REG_INIT_C	RegType := ( extTrig = > ' 0 ' , data = > ( others = > ' 0 ' ) , cnt = > ( others = > ' 0 ' ) )

Signals
r	RegType := REG_INIT_C
rin	RegType
clk	sl := ' 0 '
rst	sl := ' 1 '
axilWriteMaster	AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
axilWriteSlave	AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_INIT_C
axilReadMaster	AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
axilReadSlave	AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_INIT_C
axisMaster	AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C
axisSlave	AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C

Records
RegType

Instantiations
u_clkrst	ClkRst <Entity ClkRst>
u_dut	AxiStreamRingBuffer <Entity AxiStreamRingBuffer>
u_clkrst	ClkRst <Entity ClkRst>
u_dut	AxiStreamRingBuffer <Entity AxiStreamRingBuffer>

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The documentation for this design unit was generated from the following files:

• axi/axi-stream/tb/AxiStreamRingBufferTb.vhd
• build/SRC_VHDL/surf/AxiStreamRingBufferTb.vhd