AxiStreamRepeater.structure Architecture Reference

Architecture >> AxiStreamRepeater::structure

Processes
comb	( axisRst , inputAxisMaster , outputAxisSlaves , r )
seq	( axisClk , axisRst )
comb	( axisRst , inputAxisMaster , outputAxisSlaves , r )
seq	( axisClk , axisRst )

Constants
REG_INIT_C	RegType := ( tId = > ( others = > ' 0 ' ) , slave = > AXI_STREAM_SLAVE_INIT_C , masters = > ( others = > AXI_STREAM_MASTER_INIT_C ) )

Signals
r	RegType := REG_INIT_C
rin	RegType
inputAxisMaster	AxiStreamMasterType
inputAxisSlave	AxiStreamSlaveType
outputAxisMasters	AxiStreamMasterArray ( NUM_MASTERS_G- 1 downto 0 )
outputAxisSlaves	AxiStreamSlaveArray ( NUM_MASTERS_G- 1 downto 0 )

Records
RegType

Instantiations
u_input	AxiStreamPipeline <Entity AxiStreamPipeline>
u_output	AxiStreamPipeline <Entity AxiStreamPipeline>
u_input	AxiStreamPipeline <Entity AxiStreamPipeline>
u_output	AxiStreamPipeline <Entity AxiStreamPipeline>

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The documentation for this design unit was generated from the following files:

• axi/axi-stream/rtl/AxiStreamRepeater.vhd
• build/SRC_VHDL/surf/AxiStreamRepeater.vhd