AxiStreamRepeater Entity Reference

Inheritance diagram for AxiStreamRepeater:

Collaboration diagram for AxiStreamRepeater:

Entities
AxiStreamRepeater.structure	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_unsigned
std_logic_arith
StdRtlPkg	Package <StdRtlPkg>
AxiStreamPkg	Package <AxiStreamPkg>

Generics
TPD_G	time := 1 ns
RST_POLARITY_G	sl := ' 1 '
RST_ASYNC_G	boolean := false
NUM_MASTERS_G	positive := 2
INCR_AXIS_ID_G	boolean := false
INPUT_PIPE_STAGES_G	natural := 0
OUTPUT_PIPE_STAGES_G	natural := 0

Ports
axisClk	in	sl
axisRst	in	sl
sAxisMaster	in	AxiStreamMasterType
sAxisSlave	out	AxiStreamSlaveType
mAxisMasters	out	AxiStreamMasterArray ( NUM_MASTERS_G- 1 downto 0 )
mAxisSlaves	in	AxiStreamSlaveArray ( NUM_MASTERS_G- 1 downto 0 )

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The documentation for this design unit was generated from the following files:

• axi/axi-stream/rtl/AxiStreamRepeater.vhd
• build/SRC_VHDL/surf/AxiStreamRepeater.vhd