AxiStreamPrbsFlowCtrl.rtl Architecture Reference

Architecture >> AxiStreamPrbsFlowCtrl::rtl

Processes
comb	( pause , r , rst , rxMaster , txSlave )
seq	( clk , rst )
comb	( pause , r , rst , rxMaster , txSlave )
seq	( clk , rst )

Constants
REG_INIT_C	RegType := ( randomData = > SEED_G , rxSlave = > AXI_STREAM_SLAVE_INIT_C , txMaster = > AXI_STREAM_MASTER_INIT_C )

Signals
r	RegType := REG_INIT_C
rin	RegType
rxMaster	AxiStreamMasterType
rxSlave	AxiStreamSlaveType
txMaster	AxiStreamMasterType
txSlave	AxiStreamSlaveType
pause	sl

Records
RegType

Instantiations
u_dspcomparator	DspComparator <Entity DspComparator>
u_pipe	AxiStreamPipeline <Entity AxiStreamPipeline>
u_dspcomparator	DspComparator <Entity DspComparator>
u_pipe	AxiStreamPipeline <Entity AxiStreamPipeline>

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The documentation for this design unit was generated from the following files:

• axi/axi-stream/rtl/AxiStreamPrbsFlowCtrl.vhd
• build/SRC_VHDL/surf/AxiStreamPrbsFlowCtrl.vhd