AxiStreamPrbsFlowCtrl Entity Reference

Inheritance diagram for AxiStreamPrbsFlowCtrl:

Collaboration diagram for AxiStreamPrbsFlowCtrl:

Entities
AxiStreamPrbsFlowCtrl.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_unsigned
std_logic_arith
StdRtlPkg	Package <StdRtlPkg>
AxiStreamPkg	Package <AxiStreamPkg>

Generics
TPD_G	time := 1 ns
RST_POLARITY_G	sl := ' 1 '
RST_ASYNC_G	boolean := false
PIPE_STAGES_G	natural range 0 to 1 := 0
SEED_G	slv ( 31 downto 0 ) := x " AAAA_5555 "
PRBS_TAPS_G	NaturalArray := ( 0 = > 31 , 1 = > 6 , 2 = > 2 , 3 = > 1 )

Ports
clk	in	sl
rst	in	sl
threshold	in	slv ( 31 downto 0 ) := x " 8000_0000 "
sAxisMaster	in	AxiStreamMasterType
sAxisSlave	out	AxiStreamSlaveType
mAxisMaster	out	AxiStreamMasterType
mAxisSlave	in	AxiStreamSlaveType

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The documentation for this design unit was generated from the following files:

• axi/axi-stream/rtl/AxiStreamPrbsFlowCtrl.vhd
• build/SRC_VHDL/surf/AxiStreamPrbsFlowCtrl.vhd