AxiStreamFlushTb.testbed Architecture Reference

Architecture >> AxiStreamFlushTb::testbed

Processes
PROCESS_7	( fastClk )
PROCESS_87	( fastClk )

Constants
FAST_CLK_PERIOD_C	time := 5 ns
TPD_C	time := FAST_CLK_PERIOD_C/ 4
PRBS_SEED_SIZE_C	natural := 32
PRBS_TAPS_C	NaturalArray := ( 0 = > 31 , 1 = > 6 , 2 = > 2 , 3 = > 1 )
AXI_STREAM_CONFIG_C	AxiStreamConfigType := ssiAxiStreamConfig ( 4 )

Signals
fastClk	sl := ' 0 '
fastRst	sl := ' 1 '
obMaster	AxiStreamMasterType
obSlave	AxiStreamSlaveType
ibMaster	AxiStreamMasterType
ibCtrl	AxiStreamCtrlType
flushEn	sl
count	integer range 0 to 254

Instantiations
clkrst_fast	ClkRst <Entity ClkRst>
ssiprbstx_inst	SsiPrbsTx <Entity SsiPrbsTx>
u_flush	AxiStreamFlush <Entity AxiStreamFlush>
clkrst_fast	ClkRst <Entity ClkRst>
ssiprbstx_inst	SsiPrbsTx <Entity SsiPrbsTx>
u_flush	AxiStreamFlush <Entity AxiStreamFlush>

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The documentation for this design unit was generated from the following files:

• axi/axi-stream/tb/AxiStreamFlushTb.vhd
• build/SRC_VHDL/surf/AxiStreamFlushTb.vhd