AxiStreamDmaV2IpIntegrator.rtl Architecture Reference

Architecture >> AxiStreamDmaV2IpIntegrator::rtl

Constants
AXIS_CONFIG_C	AxiStreamConfigType := ( TSTRB_EN_C = > false , TDATA_BYTES_C = > 8 , TDEST_BITS_C = > 8 , TID_BITS_C = > 8 , TKEEP_MODE_C = > TKEEP_NORMAL_C , TUSER_BITS_C = > 2 , TUSER_MODE_C = > TUSER_FIRST_LAST_C )
AXI_CONFIG_C	AxiConfigType := axiConfig ( ADDR_WIDTH_C = > 16 , DATA_BYTES_C = > 8 , ID_BITS_C = > 8 , LEN_BITS_C = > 8 )

Signals
axiResetN	sl := ' 1 '
axilReadMaster	AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
axilReadSlave	AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_INIT_C
axilWriteMaster	AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
axilWriteSlave	AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_INIT_C
sAxisMasters	AxiStreamMasterArray ( 0 downto 0 ) := ( others = > AXI_STREAM_MASTER_INIT_C )
sAxisSlaves	AxiStreamSlaveArray ( 0 downto 0 ) := ( others = > AXI_STREAM_SLAVE_INIT_C )
mAxisMasters	AxiStreamMasterArray ( 0 downto 0 ) := ( others = > AXI_STREAM_MASTER_INIT_C )
mAxisSlaves	AxiStreamSlaveArray ( 0 downto 0 ) := ( others = > AXI_STREAM_SLAVE_INIT_C )
mAxisCtrl	AxiStreamCtrlArray ( 0 downto 0 ) := ( others = > AXI_STREAM_CTRL_UNUSED_C )
axiReadMasters	AxiReadMasterArray ( 1 downto 0 ) := ( others = > AXI_READ_MASTER_INIT_C )
axiReadSlaves	AxiReadSlaveArray ( 1 downto 0 ) := ( others = > AXI_READ_SLAVE_INIT_C )
axiWriteMasters	AxiWriteMasterArray ( 1 downto 0 ) := ( others = > AXI_WRITE_MASTER_INIT_C )
axiWriteSlaves	AxiWriteSlaveArray ( 1 downto 0 ) := ( others = > AXI_WRITE_SLAVE_INIT_C )
axiWriteCtrl	AxiCtrlArray ( 1 downto 0 ) := ( others = > AXI_CTRL_INIT_C )
onlineVec	slv ( 0 downto 0 )
acknowledgeVec	slv ( 0 downto 0 )

Instantiations
u_axil	SlaveAxiLiteIpIntegrator <Entity SlaveAxiLiteIpIntegrator>
u_dut	AxiStreamDmaV2 <Entity AxiStreamDmaV2>

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The documentation for this design unit was generated from the following file:

• axi/dma/ip_integrator/AxiStreamDmaV2IpIntegrator.vhd