AxiStreamDmaIpIntegrator.rtl Architecture Reference

Architecture >> AxiStreamDmaIpIntegrator::rtl

Constants
AXIS_CONFIG_C	AxiStreamConfigType := ( TSTRB_EN_C = > false , TDATA_BYTES_C = > 4 , TDEST_BITS_C = > 1 , TID_BITS_C = > 1 , TKEEP_MODE_C = > TKEEP_NORMAL_C , TUSER_BITS_C = > 2 , TUSER_MODE_C = > TUSER_FIRST_LAST_C )
AXI_CONFIG_C	AxiConfigType := axiConfig ( ADDR_WIDTH_C = > 16 , DATA_BYTES_C = > 4 , ID_BITS_C = > 1 , LEN_BITS_C = > 8 )

Signals
axilResetN	sl := ' 1 '
axilReadMasters	AxiLiteReadMasterArray ( 0 downto 0 ) := ( others = > AXI_LITE_READ_MASTER_INIT_C )
axilReadSlaves	AxiLiteReadSlaveArray ( 0 downto 0 ) := ( others = > AXI_LITE_READ_SLAVE_INIT_C )
axilWriteMasters	AxiLiteWriteMasterArray ( 0 downto 0 ) := ( others = > AXI_LITE_WRITE_MASTER_INIT_C )
axilWriteSlaves	AxiLiteWriteSlaveArray ( 0 downto 0 ) := ( others = > AXI_LITE_WRITE_SLAVE_INIT_C )

Instantiations
u_axil	SlaveAxiLiteIpIntegrator <Entity SlaveAxiLiteIpIntegrator>
u_dut	AxiStreamDma <Entity AxiStreamDma>

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The documentation for this design unit was generated from the following file:

• axi/dma/ip_integrator/AxiStreamDmaIpIntegrator.vhd