AxiStreamDepacketizer.rtl Architecture Reference

Architecture >> AxiStreamDepacketizer::rtl

Processes
comb	( axisRst , inputAxisMaster , outputAxisSlave , r , restart )
seq	( axisClk , axisRst )
comb	( axisRst , inputAxisMaster , outputAxisSlave , r , restart )
seq	( axisClk , axisRst )

Constants
AXIS_CONFIG_C	AxiStreamConfigType := ( TSTRB_EN_C = > false , TDATA_BYTES_C = > 8 , TDEST_BITS_C = > 8 , TID_BITS_C = > 8 , TKEEP_MODE_C = > TKEEP_NORMAL_C , TUSER_BITS_C = > 8 , TUSER_MODE_C = > TUSER_FIRST_LAST_C )
VERSION_C	slv ( 3 downto 0 ) := " 0000 "
REG_INIT_C	RegType := ( state = > HEADER_S , frameNumber = > ( others = > ' 0 ' ) , packetNumber = > ( others = > ' 0 ' ) , sof = > ' 1 ' , startup = > ' 1 ' , sideband = > ' 0 ' , inputAxisSlave = > AXI_STREAM_SLAVE_INIT_C , outputAxisMaster = > ( others = > axiStreamMasterInit ( AXIS_CONFIG_C ) ) )

Types
StateType	( HEADER_S , BLEED_S , MOVE_S , DONE_S )

Signals
r	RegType := REG_INIT_C
rin	RegType
inputAxisMaster	AxiStreamMasterType
inputAxisSlave	AxiStreamSlaveType
outputAxisMaster	AxiStreamMasterType
outputAxisSlave	AxiStreamSlaveType

Records
RegType

Instantiations
u_axistreampipeline_input	AxiStreamPipeline <Entity AxiStreamPipeline>
u_axistreampipeline_output	AxiStreamPipeline <Entity AxiStreamPipeline>
u_axistreampipeline_input	AxiStreamPipeline <Entity AxiStreamPipeline>
u_axistreampipeline_output	AxiStreamPipeline <Entity AxiStreamPipeline>

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/AxiStreamDepacketizer.vhd
• protocols/packetizer/rtl/AxiStreamDepacketizer.vhd