AxiStreamDepacketizer Entity Reference

Inheritance diagram for AxiStreamDepacketizer:

Collaboration diagram for AxiStreamDepacketizer:

Entities
AxiStreamDepacketizer.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_unsigned
std_logic_arith
StdRtlPkg	Package <StdRtlPkg>
AxiStreamPkg	Package <AxiStreamPkg>
SsiPkg	Package <SsiPkg>

Generics
TPD_G	time := 1 ns
RST_ASYNC_G	boolean := false
INPUT_PIPE_STAGES_G	integer := 0
OUTPUT_PIPE_STAGES_G	integer := 0

Ports
axisClk	in	sl
axisRst	in	sl
restart	in	sl := ' 0 '
sAxisMaster	in	AxiStreamMasterType
sAxisSlave	out	AxiStreamSlaveType
mAxisMaster	out	AxiStreamMasterType
mAxisSlave	in	AxiStreamSlaveType

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/AxiStreamDepacketizer.vhd
• protocols/packetizer/rtl/AxiStreamDepacketizer.vhd