AxiStreamBytePackerTb.test Architecture Reference

Architecture >> AxiStreamBytePackerTb::test

Constants
SRC_CONFIG_C	AxiStreamConfigType := ( TSTRB_EN_C = > false , TDATA_BYTES_C = > 16 , TDEST_BITS_C = > 0 , TID_BITS_C = > 0 , TKEEP_MODE_C = > TKEEP_COMP_C , TUSER_BITS_C = > 2 , TUSER_MODE_C = > TUSER_FIRST_LAST_C )
DST_CONFIG_C	AxiStreamConfigType := ( TSTRB_EN_C = > false , TDATA_BYTES_C = > 16 , TDEST_BITS_C = > 0 , TID_BITS_C = > 0 , TKEEP_MODE_C = > TKEEP_COMP_C , TUSER_BITS_C = > 2 , TUSER_MODE_C = > TUSER_FIRST_LAST_C )
CLK_PERIOD_C	time := 5 . 000 ns
TPD_G	time := 1 ns

Signals
axiClk	sl
axiRst	sl
testInMaster	AxiStreamMasterArray ( 15 downto 0 )
testOutMaster	AxiStreamMasterArray ( 15 downto 0 )
testFail	slv ( 15 downto 0 )

Instantiations
u_clkrst	ClkRst <Entity ClkRst>
u_packtx	AxiStreamBytePackerTbTx <Entity AxiStreamBytePackerTbTx>
u_pack	AxiStreamBytePacker <Entity AxiStreamBytePacker>
u_packrx	AxiStreamBytePackerTbRx <Entity AxiStreamBytePackerTbRx>
u_clkrst	ClkRst <Entity ClkRst>
u_packtx	AxiStreamBytePackerTbTx <Entity AxiStreamBytePackerTbTx>
u_pack	AxiStreamBytePacker <Entity AxiStreamBytePacker>
u_packrx	AxiStreamBytePackerTbRx <Entity AxiStreamBytePackerTbRx>

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The documentation for this design unit was generated from the following files:

• axi/axi-stream/tb/AxiStreamBytePackerTb.vhd
• build/SRC_VHDL/surf/AxiStreamBytePackerTb.vhd