Architecture >> AxiStreamBytePackerTb::test

Constants
SWEEP_SIZE_C	positive := 4
SRC_CONFIG_C	AxiStreamConfigType := ( TSTRB_EN_C = > false , TDATA_BYTES_C = > SWEEP_SIZE_C , TDEST_BITS_C = > 0 , TID_BITS_C = > 0 , TKEEP_MODE_C = > TKEEP_COMP_C , TUSER_BITS_C = > 2 , TUSER_MODE_C = > TUSER_FIRST_LAST_C )
DST_CONFIG_C	AxiStreamConfigType := ( TSTRB_EN_C = > false , TDATA_BYTES_C = > 2 * SWEEP_SIZE_C , TDEST_BITS_C = > 0 , TID_BITS_C = > 0 , TKEEP_MODE_C = > TKEEP_COMP_C , TUSER_BITS_C = > 2 , TUSER_MODE_C = > TUSER_FIRST_LAST_C )
CLK_PERIOD_C	time := 5 . 000 ns
TPD_C	time := 1 ns

Signals
axiClk	sl := ' 0 '
axiRst	sl := ' 0 '
testInMaster	AxiStreamMasterArray ( SWEEP_SIZE_C- 1 downto 0 ) := ( others = > AXI_STREAM_MASTER_INIT_C )
testOutMaster	AxiStreamMasterArray ( SWEEP_SIZE_C- 1 downto 0 ) := ( others = > AXI_STREAM_MASTER_INIT_C )
testFail	slv ( SWEEP_SIZE_C- 1 downto 0 ) := ( others = > ' 0 ' )

Instantiations
u_clkrst	ClkRst <Entity ClkRst>
u_packtx	AxiStreamBytePackerTbTx <Entity AxiStreamBytePackerTbTx>
u_pack	AxiStreamBytePacker <Entity AxiStreamBytePacker>
u_packrx	AxiStreamBytePackerTbRx <Entity AxiStreamBytePackerTbRx>
u_clkrst	ClkRst <Entity ClkRst>
u_packtx	AxiStreamBytePackerTbTx <Entity AxiStreamBytePackerTbTx>
u_pack	AxiStreamBytePacker <Entity AxiStreamBytePacker>
u_packrx	AxiStreamBytePackerTbRx <Entity AxiStreamBytePackerTbRx>

The documentation for this design unit was generated from the following files:

Constants

Signals