Architecture >> AxiStreamBatcherEventBuilderWrapper::rtl

Functions
slv	route1 ( mode: in natural )

Processes
comb	( M_AXIS_TREADY , S0_AXIS_TDATA , S0_AXIS_TDEST , S0_AXIS_TID , S0_AXIS_TKEEP , S0_AXIS_TLAST , S0_AXIS_TUSER , S0_AXIS_TVALID , S1_AXIS_TDATA , S1_AXIS_TDEST , S1_AXIS_TID , S1_AXIS_TKEEP , S1_AXIS_TLAST , S1_AXIS_TUSER , S1_AXIS_TVALID , mAxisMaster , sAxisSlaves )

Constants
NUM_SLAVES_C	positive := 2
AXIS_CONFIG_C	AxiStreamConfigType := ( TSTRB_EN_C = > false , TDATA_BYTES_C = > DATA_BYTES_G , TDEST_BITS_C = > 8 , TID_BITS_C = > 0 , TKEEP_MODE_C = > TKEEP_NORMAL_C , TUSER_BITS_C = > 8 , TUSER_MODE_C = > TUSER_FIRST_LAST_C )
TDEST_ROUTES_C	Slv8Array ( NUM_SLAVES_C- 1 downto 0 ) := ( 0 = > " -------- " , 1 = > route1 ( ROUTE_MODE_G ) )

Signals
axilRstN	sl
axilClk	sl
axilRst	sl
axilReadMaster	AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
axilReadSlave	AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_INIT_C
axilWriteMaster	AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
axilWriteSlave	AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_INIT_C
sAxisMasters	AxiStreamMasterArray ( NUM_SLAVES_C- 1 downto 0 ) := ( others = > AXI_STREAM_MASTER_INIT_C )
sAxisSlaves	AxiStreamSlaveArray ( NUM_SLAVES_C- 1 downto 0 ) := ( others = > AXI_STREAM_SLAVE_INIT_C )
mAxisMaster	AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C
mAxisSlave	AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C

Instantiations
u_axil	SlaveAxiLiteIpIntegrator <Entity SlaveAxiLiteIpIntegrator>
u_dut	AxiStreamBatcherEventBuilder <Entity AxiStreamBatcherEventBuilder>

The documentation for this design unit was generated from the following file:

Functions

Processes