AxiSpiMaster.rtl Architecture Reference

Architecture >> AxiSpiMaster::rtl

Processes
comb	( axiReadMaster , axiRst , axiWriteMaster , memData , r , rdData , rdEn )
seq	( axiClk )

Constants
PACKET_SIZE_C	positive := ite ( MODE_G = " RW " , 1 , 0 ) + ADDRESS_SIZE_G+ DATA_SIZE_G
CHIP_BITS_C	integer := log2 ( SPI_NUM_CHIPS_G )
REG_INIT_C	RegType := ( state = > WAIT_AXI_TXN_S , axiReadSlave = > AXI_LITE_READ_SLAVE_INIT_C , axiWriteSlave = > AXI_LITE_WRITE_SLAVE_INIT_C , wrData = > ( others = > ' 0 ' ) , chipSel = > ( others = > ' 0 ' ) , wrEn = > ' 0 ' )

Types
StateType	( WAIT_AXI_TXN_S , WAIT_CYCLE_S , WAIT_CYCLE_SHADOW_S , WAIT_SPI_TXN_DONE_S , SHADOW_READ_DONE_S )

Signals
rdData	slv ( PACKET_SIZE_C- 1 downto 0 )
rdEn	sl
memData	slv ( DATA_SIZE_G- 1 downto 0 ) := ( others = > ' 0 ' )
r	RegType := REG_INIT_C
rin	RegType
csb	slv ( SPI_NUM_CHIPS_G- 1 downto 0 )

Records
RegType

Instantiations
u_dualportram_1	DualPortRam <Entity DualPortRam>
spimaster_1	SpiMaster <Entity SpiMaster>

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The documentation for this design unit was generated from the following file:

• protocols/spi/rtl/AxiSpiMaster.vhd