AxiSpiMaster Entity Reference

Inheritance diagram for AxiSpiMaster:

Collaboration diagram for AxiSpiMaster:

Entities
AxiSpiMaster.rtl	architecture

Libraries
ieee
unisim
surf

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned
vcomponents
StdRtlPkg	Package <StdRtlPkg>
AxiLitePkg	Package <AxiLitePkg>

Generics
TPD_G	time := 1 ns
ADDRESS_SIZE_G	natural := 15
DATA_SIZE_G	natural := 8
MODE_G	string := " RW "
SHADOW_EN_G	boolean := false
SHADOW_MEM_TYPE_G	string := " block "
CPHA_G	sl := ' 0 '
CPOL_G	sl := ' 0 '
CLK_PERIOD_G	real := 6 . 4E - 9
SPI_SCLK_PERIOD_G	real := 100 . 0E - 6
SPI_NUM_CHIPS_G	positive := 1

Ports
axiClk	in	sl
axiRst	in	sl
axiReadMaster	in	AxiLiteReadMasterType
axiReadSlave	out	AxiLiteReadSlaveType
axiWriteMaster	in	AxiLiteWriteMasterType
axiWriteSlave	out	AxiLiteWriteSlaveType
shadowAddr	in	slv ( ite ( SPI_NUM_CHIPS_G = 1 , 0 , log2 ( SPI_NUM_CHIPS_G ) ) + ADDRESS_SIZE_G- 1 downto 0 ) := ( others = > ' 0 ' )
shadowData	out	slv ( DATA_SIZE_G- 1 downto 0 ) := ( others = > ' 0 ' )
coreSclk	out	sl
coreSDin	in	sl
coreSDout	out	sl
coreCsb	out	sl
coreMCsb	out	slv ( SPI_NUM_CHIPS_G- 1 downto 0 )

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The documentation for this design unit was generated from the following file:

• protocols/spi/rtl/AxiSpiMaster.vhd