AxiLiteToSaci2 Entity Reference

Inheritance diagram for AxiLiteToSaci2:

Collaboration diagram for AxiLiteToSaci2:

Entities
AxiLiteToSaci2.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_unsigned
std_logic_arith
StdRtlPkg	Package <StdRtlPkg>
AxiLitePkg	Package <AxiLitePkg>

Generics
TPD_G	time := 1 ns
AXIL_CLK_PERIOD_G	real := 8 . 0E - 9
AXIL_TIMEOUT_G	real := 1 . 0E - 3
SACI_CLK_PERIOD_G	real := 1 . 0E - 6
SACI_CLK_FREERUN_G	boolean := false
SACI_ADDR_BITS_G	integer range 2 to 30 := 24
SACI_NUM_CHIPS_G	positive := 1
SACI_RSP_BUSSED_G	boolean := false

Ports
saciClk	out	sl
saciCmd	out	sl
saciSelL	out	slv ( SACI_NUM_CHIPS_G- 1 downto 0 )
saciRsp	in	slv ( ite ( SACI_RSP_BUSSED_G , 0 , SACI_NUM_CHIPS_G- 1 ) downto 0 )
saciBusReq	out	sl
saciBusGr	in	sl := ' 1 '
asicRstL	in	sl := ' 1 '
axilClk	in	sl
axilRst	in	sl
axilReadMaster	in	AxiLiteReadMasterType
axilReadSlave	out	AxiLiteReadSlaveType
axilWriteMaster	in	AxiLiteWriteMasterType
axilWriteSlave	out	AxiLiteWriteSlaveType

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/AxiLiteToSaci2.vhd
• protocols/saci/saci2/rtl/AxiLiteToSaci2.vhd