AxiLiteToSaci2.rtl Architecture Reference

Architecture >> AxiLiteToSaci2::rtl

Processes
comb	( ack , asicRstL , axilReadMaster , axilRst , axilWriteMaster , fail , r , rdData , saciBusGr )
seq	( axilClk )
comb	( ack , asicRstL , axilReadMaster , axilRst , axilWriteMaster , fail , r , rdData , saciBusGr )
seq	( axilClk )

Constants
CHIP_BITS_C	integer := log2 ( SACI_NUM_CHIPS_G )
TIMEOUT_C	integer := integer ( AXIL_TIMEOUT_G/ AXIL_CLK_PERIOD_G ) - 1
REG_INIT_C	RegType := ( state = > IDLE_S , saciBusReq = > ' 0 ' , saciRst = > ' 1 ' , req = > ' 0 ' , chip = > ( others = > ' 0 ' ) , op = > ' 0 ' , addr = > ( others = > ' 0 ' ) , wrData = > ( others = > ' 0 ' ) , timer = > 0 , axilReadSlave = > AXI_LITE_READ_SLAVE_INIT_C , axilWriteSlave = > AXI_LITE_WRITE_SLAVE_INIT_C )

Types
StateType	( IDLE_S , SACI_REQ_S , SACI_ACK_S )

Signals
r	RegType := REG_INIT_C
rin	RegType
ack	sl
fail	sl
rdData	slv ( 31 downto 0 )

Records
RegType

Instantiations
u_saci2coordinator_1	Saci2Coordinator <Entity Saci2Coordinator>
u_saci2coordinator_1	Saci2Coordinator <Entity Saci2Coordinator>

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/AxiLiteToSaci2.vhd
• protocols/saci/saci2/rtl/AxiLiteToSaci2.vhd