AxiLiteToIpBus.rtl Architecture Reference

Architecture >> AxiLiteToIpBus::rtl

Processes
comb	( ipbAck , ipbErr , ipbRdata , r , req , rst )
seq	( clk )
comb	( ipbAck , ipbErr , ipbRdata , r , req , rst )
seq	( clk )

Constants
REG_INIT_C	RegType := ( ipbAddr = > ( others = > ' 0 ' ) , ipbWdata = > ( others = > ' 0 ' ) , ipbStrobe = > ' 0 ' , ipbWrite = > ' 0 ' , ack = > AXI_LITE_ACK_INIT_C , state = > IDLE_S )

Types
StateType	( IDLE_S , WAIT_S )

Signals
r	RegType := REG_INIT_C
rin	RegType
req	AxiLiteReqType
ack	AxiLiteAckType

Records
RegType

Instantiations
u_axiliteslave	AxiLiteSlave <Entity AxiLiteSlave>
u_axiliteslave	AxiLiteSlave <Entity AxiLiteSlave>

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The documentation for this design unit was generated from the following files:

• axi/bridge/rtl/AxiLiteToIpBus.vhd
• build/SRC_VHDL/surf/AxiLiteToIpBus.vhd