AxiLiteRamSyncStatusVectorIpIntegrator.rtl Architecture Reference

Architecture >> AxiLiteRamSyncStatusVectorIpIntegrator::rtl

Signals
axilResetN	sl := ' 1 '
axilReadMaster	AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
axilReadSlave	AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_INIT_C
axilWriteMaster	AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
axilWriteSlave	AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_INIT_C

Instantiations
u_axil	SlaveAxiLiteIpIntegrator <Entity SlaveAxiLiteIpIntegrator>
u_dut	AxiLiteRamSyncStatusVector <Entity AxiLiteRamSyncStatusVector>

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The documentation for this design unit was generated from the following file:

• axi/axi-lite/ip_integrator/AxiLiteRamSyncStatusVectorIpIntegrator.vhd