AxiLiteFifoPush.structure Architecture Reference

Architecture >> AxiLiteFifoPush::structure

Processes
comb	( axiClkRst , axiReadMaster , axiWriteMaster , ipushFifoAFull , ipushFifoFull , r )
seq	( axiClk , axiClkRst )
comb	( axiClkRst , axiReadMaster , axiWriteMaster , ipushFifoAFull , ipushFifoFull , r )
seq	( axiClk , axiClkRst )

Constants
PUSH_SIZE_C	integer := bitSize ( PUSH_FIFO_COUNT_G- 1 )
PUSH_COUNT_C	integer := 2 ** PUSH_SIZE_C
REG_INIT_C	RegType := ( pushFifoWrite = > ( others = > ' 0 ' ) , pushFifoDin = > ( others = > ' 0 ' ) , axiReadSlave = > AXI_LITE_READ_SLAVE_INIT_C , axiWriteSlave = > AXI_LITE_WRITE_SLAVE_INIT_C )

Signals
ipushFifoFull	slv ( PUSH_COUNT_C- 1 downto 0 )
ipushFifoAFull	slv ( PUSH_COUNT_C- 1 downto 0 )
ipushFifoDin	Slv ( 35 downto 0 )
ipushFifoWrite	slv ( PUSH_COUNT_C- 1 downto 0 )
r	RegType := REG_INIT_C
rin	RegType

Records
RegType

Instantiations
u_fifo	FifoCascade <Entity FifoCascade>
u_fifo	FifoCascade <Entity FifoCascade>

---

The documentation for this design unit was generated from the following files:

• axi/axi-lite/rtl/AxiLiteFifoPush.vhd
• build/SRC_VHDL/surf/AxiLiteFifoPush.vhd