AxiLiteFifoPush Entity Reference

Inheritance diagram for AxiLiteFifoPush:

Collaboration diagram for AxiLiteFifoPush:

Entities
AxiLiteFifoPush.structure	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned
StdRtlPkg	Package <StdRtlPkg>
AxiLitePkg	Package <AxiLitePkg>

Generics
TPD_G	time := 1 ns
RST_POLARITY_G	sl := ' 1 '
RST_ASYNC_G	boolean := false
PUSH_FIFO_COUNT_G	positive := 1
PUSH_SYNC_FIFO_G	boolean := false
PUSH_MEMORY_TYPE_G	string := " distributed "
PUSH_ADDR_WIDTH_G	integer range 4 to 48 := 4

Ports
axiClk	in	sl
axiClkRst	in	sl
axiReadMaster	in	AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
axiReadSlave	out	AxiLiteReadSlaveType
axiWriteMaster	in	AxiLiteWriteMasterType
axiWriteSlave	out	AxiLiteWriteSlaveType
pushFifoAFull	out	slv ( PUSH_FIFO_COUNT_G- 1 downto 0 )
pushFifoClk	in	slv ( PUSH_FIFO_COUNT_G- 1 downto 0 )
pushFifoRst	in	slv ( PUSH_FIFO_COUNT_G- 1 downto 0 )
pushFifoValid	out	slv ( PUSH_FIFO_COUNT_G- 1 downto 0 )
pushFifoDout	out	Slv36Array ( PUSH_FIFO_COUNT_G- 1 downto 0 )
pushFifoRead	in	slv ( PUSH_FIFO_COUNT_G- 1 downto 0 )

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The documentation for this design unit was generated from the following file:

• axi/axi-lite/rtl/AxiLiteFifoPush.vhd