AxiLiteFifoPop.structure Architecture Reference

Architecture >> AxiLiteFifoPop::structure

Processes
comb	( axiClkRst , axiReadMaster , axiWriteMaster , iloopFifoDout , iloopFifoValid , ipopFifoDout , ipopFifoValid , r )
seq	( axiClk , axiClkRst )
comb	( axiClkRst , axiReadMaster , axiWriteMaster , iloopFifoDout , iloopFifoValid , ipopFifoDout , ipopFifoValid , r )
seq	( axiClk , axiClkRst )

Constants
POP_SIZE_C	integer := bitSize ( POP_FIFO_COUNT_G- 1 )
POP_COUNT_C	integer := 2 ** POP_SIZE_C
LOOP_SIZE_C	integer := bitSize ( LOOP_FIFO_COUNT_G- 1 )
LOOP_COUNT_C	integer := 2 ** LOOP_SIZE_C
REG_INIT_C	RegType := ( loopFifoDin = > ( others = > ' 0 ' ) , loopFifoWrite = > ( others = > ' 0 ' ) , loopFifoRead = > ( others = > ' 0 ' ) , popFifoRead = > ( others = > ' 0 ' ) , axiReadSlave = > AXI_LITE_READ_SLAVE_INIT_C , axiWriteSlave = > AXI_LITE_WRITE_SLAVE_INIT_C )

Signals
ipopFifoValid	slv ( POP_COUNT_C- 1 downto 0 )
ipopFifoDout	Slv32Array ( POP_COUNT_C- 1 downto 0 )
ipopFifoRead	slv ( POP_COUNT_C- 1 downto 0 )
iloopFifoDin	slv ( 31 downto 0 )
iloopFifoWrite	Slv ( LOOP_COUNT_C- 1 downto 0 )
iloopFifoValid	slv ( LOOP_COUNT_C- 1 downto 0 )
iloopFifoDout	Slv32Array ( LOOP_COUNT_C- 1 downto 0 )
iloopFifoRead	slv ( LOOP_COUNT_C- 1 downto 0 )
r	RegType := REG_INIT_C
rin	RegType

Records
RegType

Instantiations
u_fifo	FifoCascade <Entity FifoCascade>
u_fifo	FifoCascade <Entity FifoCascade>
u_fifo	FifoCascade <Entity FifoCascade>
u_fifo	FifoCascade <Entity FifoCascade>

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The documentation for this design unit was generated from the following files:

• axi/axi-lite/rtl/AxiLiteFifoPop.vhd
• build/SRC_VHDL/surf/AxiLiteFifoPop.vhd