AxiLiteFifoPop Entity Reference

Inheritance diagram for AxiLiteFifoPop:

Collaboration diagram for AxiLiteFifoPop:

Entities
AxiLiteFifoPop.structure	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned
StdRtlPkg	Package <StdRtlPkg>
AxiLitePkg	Package <AxiLitePkg>

Generics
TPD_G	time := 1 ns
RST_ASYNC_G	boolean := false
POP_FIFO_COUNT_G	positive := 1
POP_SYNC_FIFO_G	boolean := false
POP_MEMORY_TYPE_G	string := " block "
POP_ADDR_WIDTH_G	integer range 4 to 48 := 4
POP_FULL_THRES_G	integer range 1 to ( 2 ** 24 ) := 1
LOOP_FIFO_EN_G	boolean := false
LOOP_FIFO_COUNT_G	positive := 1
LOOP_MEMORY_TYPE_G	string := " block "
LOOP_ADDR_WIDTH_G	integer range 4 to 48 := 4
RANGE_LSB_G	integer range 0 to 31 := 8
VALID_POSITION_G	integer range 0 to 31 := 0
VALID_POLARITY_G	sl := ' 0 '

Ports
axiClk	in	sl
axiClkRst	in	sl
axiReadMaster	in	AxiLiteReadMasterType
axiReadSlave	out	AxiLiteReadSlaveType
axiWriteMaster	in	AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
axiWriteSlave	out	AxiLiteWriteSlaveType
popFifoValid	out	slv ( POP_FIFO_COUNT_G- 1 downto 0 )
popFifoAEmpty	out	slv ( POP_FIFO_COUNT_G- 1 downto 0 )
loopFifoValid	out	slv ( LOOP_FIFO_COUNT_G- 1 downto 0 )
loopFifoAEmpty	out	slv ( LOOP_FIFO_COUNT_G- 1 downto 0 )
loopFifoAFull	out	slv ( LOOP_FIFO_COUNT_G- 1 downto 0 )
popFifoClk	in	slv ( POP_FIFO_COUNT_G- 1 downto 0 )
popFifoRst	in	slv ( POP_FIFO_COUNT_G- 1 downto 0 )
popFifoWrite	in	slv ( POP_FIFO_COUNT_G- 1 downto 0 )
popFifoDin	in	Slv32Array ( POP_FIFO_COUNT_G- 1 downto 0 )
popFifoFull	out	slv ( POP_FIFO_COUNT_G- 1 downto 0 )
popFifoAFull	out	slv ( POP_FIFO_COUNT_G- 1 downto 0 )
popFifoPFull	out	slv ( POP_FIFO_COUNT_G- 1 downto 0 )

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The documentation for this design unit was generated from the following files:

• axi/axi-lite/rtl/AxiLiteFifoPop.vhd
• build/SRC_VHDL/surf/AxiLiteFifoPop.vhd