SURF
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AxiI2cEepromCore Entity Reference
+ Inheritance diagram for AxiI2cEepromCore:
+ Collaboration diagram for AxiI2cEepromCore:

Entities

AxiI2cEepromCore.rtl  architecture
 

Libraries

ieee 
surf 

Use Clauses

std_logic_1164 
std_logic_unsigned 
std_logic_arith 
StdRtlPkg  Package <StdRtlPkg>
AxiLitePkg  Package <AxiLitePkg>
I2cPkg  Package <I2cPkg>

Generics

TPD_G  time := 1 ns
ADDR_WIDTH_G  positive := 16
POLL_TIMEOUT_G  positive := 16
I2C_ADDR_G  slv ( 6 downto 0 ) := " 1010000 "
I2C_SCL_FREQ_G  real := 100 . 0E + 3
I2C_MIN_PULSE_G  real := 100 . 0E - 9
AXI_CLK_FREQ_G  real := 156 . 25E + 6

Ports

i2ci   in   i2c_in_type
i2co   out   i2c_out_type
axilReadMaster   in   AxiLiteReadMasterType
axilReadSlave   out   AxiLiteReadSlaveType
axilWriteMaster   in   AxiLiteWriteMasterType
axilWriteSlave   out   AxiLiteWriteSlaveType
axilClk   in   sl
axilRst   in   sl

The documentation for this design unit was generated from the following files: