Architecture >> AxiI2cEepromCore::rtl

Processes
comb	( axilReadMaster , axilRst , axilWriteMaster , r , regOut )
seq	( axilClk )
comb	( axilReadMaster , axilRst , axilWriteMaster , r , regOut )
seq	( axilClk )

Constants
I2C_SCL_5xFREQ_C	*real := 5 . 0 I2C_SCL_FREQ_G**
PRESCALE_C	natural := ( getTimeRatio ( AXI_CLK_FREQ_G , I2C_SCL_5xFREQ_C ) ) - 1
FILTER_C	*natural := natural ( AXI_CLK_FREQ_G I2C_MIN_PULSE_G ) + 1**
ADDR_SIZE_C	slv ( 1 downto 0 ) := toSlv ( wordCount ( ADDR_WIDTH_G , 8 ) - 1 , 2 )
DATA_SIZE_C	slv ( 1 downto 0 ) := toSlv ( wordCount ( 32 , 8 ) - 1 , 2 )
I2C_ADDR_C	slv ( 9 downto 0 ) := ( " 000 " & I2C_ADDR_G )
TIMEOUT_C	natural := ( getTimeRatio ( AXI_CLK_FREQ_G , 200 . 0 ) ) - 1
MY_I2C_REG_MASTER_IN_INIT_C	I2cRegMasterInType := ( i2cAddr = > I2C_ADDR_C , tenbit = > ' 0 ' , regAddr = > ( others = > ' 0 ' ) , regWrData = > ( others = > ' 0 ' ) , regOp = > ' 0 ' , regAddrSkip = > ' 0 ' , regAddrSize = > ADDR_SIZE_C , regDataSize = > DATA_SIZE_C , regReq = > ' 0 ' , busReq = > ' 0 ' , endianness = > ' 1 ' , repeatStart = > ' 0 ' , wrDataOnRd = > ' 0 ' )
REG_INIT_C	RegType := ( timer = > 0 , RnW = > ' 0 ' , axilReadSlave = > AXI_LITE_READ_SLAVE_INIT_C , axilWriteSlave = > AXI_LITE_WRITE_SLAVE_INIT_C , regIn = > MY_I2C_REG_MASTER_IN_INIT_C , state = > IDLE_S )

Types
StateType	( IDLE_S , READ_ACK_S , READ_DONE_S , WRITE_REQ_S , WRITE_ACK_S , WRITE_DONE_S , WAIT_S )

Records
RegType

Instantiations
u_i2cregmaster	I2cRegMaster <Entity I2cRegMaster>
u_i2cregmaster	I2cRegMaster <Entity I2cRegMaster>

The documentation for this design unit was generated from the following files:

Processes

Constants