AxiDac7654Reg Entity Reference

Inheritance diagram for AxiDac7654Reg:

Entities
AxiDac7654Reg.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_unsigned
std_logic_arith
StdRtlPkg	Package <StdRtlPkg>
AxiLitePkg	Package <AxiLitePkg>
AxiDac7654Pkg	Package <AxiDac7654Pkg>

Generics
TPD_G	time := 1 ns
STATUS_CNT_WIDTH_G	natural range 1 to 32 := 32

Ports
axiClk	in	sl
axiRst	in	sl
axiReadMaster	in	AxiLiteReadMasterType
axiReadSlave	out	AxiLiteReadSlaveType
axiWriteMaster	in	AxiLiteWriteMasterType
axiWriteSlave	out	AxiLiteWriteSlaveType
status	in	AxiDac7654StatusType
config	out	AxiDac7654ConfigType

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The documentation for this design unit was generated from the following file:

• devices/Ti/dac7654/rtl/AxiDac7654Reg.vhd