AxiDac7654Reg.rtl Architecture Reference

Architecture >> AxiDac7654Reg::rtl

Processes
comb	( axiReadMaster , axiRst , axiWriteMaster , r , syncIn )
seq	( axiClk )

Constants
REG_INIT_C	RegType := ( AXI_DAC7654_CONFIG_INIT_C , IDLE_S , AXI_LITE_READ_SLAVE_INIT_C , AXI_LITE_WRITE_SLAVE_INIT_C )

Types
StateType	( IDLE_S , REQ_S , ACK_S )

Signals
r	RegType := REG_INIT_C
rin	RegType
syncIn	AxiDac7654StatusType := AXI_DAC7654_STATUS_INIT_C

Records
RegType

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The documentation for this design unit was generated from the following file:

• devices/Ti/dac7654/rtl/AxiDac7654Reg.vhd