Architecture >> AxiAds42lb69Reg::rtl

Processes
comb	( adcRst , axiReadMaster , axiRst , axiWriteMaster , r , ra , regIn )
seq	( axiClk )
seqa	( adcClk )

Constants
TIMEOUT_1S_C	natural := ite ( SIM_SPEEDUP_G , 1000 , getTimeRatio ( ADC_CLK_FREQ_G , 1 . 0E + 00 ) )
REG_INIT_C	RegType := ( adcSmpl = > ( others = > ( others = > ( others = > ' 0 ' ) ) ) , regOut = > AXI_ADS42LB69_CONFIG_INIT_C , axiReadSlave = > AXI_LITE_READ_SLAVE_INIT_C , axiWriteSlave = > AXI_LITE_WRITE_SLAVE_INIT_C )
ADC_INIT_C	AdcType := ( timer = > 0 , smplCnt = > 0 , armed = > ' 0 ' )

Signals
r	RegType := REG_INIT_C
rin	RegType
ra	AdcType := ADC_INIT_C
rain	AdcType
regIn	AxiAds42lb69StatusType := AXI_ADS42LB69_STATUS_INIT_C

Instantiations
syncout_delayin_data	SynchronizerFifo <Entity SynchronizerFifo>

The documentation for this design unit was generated from the following file:

Processes

Constants