AxiAds42lb69Reg Entity Reference

Inheritance diagram for AxiAds42lb69Reg:

Collaboration diagram for AxiAds42lb69Reg:

Entities
AxiAds42lb69Reg.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_unsigned
std_logic_arith
StdRtlPkg	Package <StdRtlPkg>
AxiLitePkg	Package <AxiLitePkg>
AxiAds42lb69Pkg	Package <AxiAds42lb69Pkg>

Generics
TPD_G	time := 1 ns
SIM_SPEEDUP_G	boolean := false
ADC_CLK_FREQ_G	real := 250 . 00E + 6
DMODE_INIT_G	slv ( 1 downto 0 ) := " 00 "

Ports
axiReadMaster	in	AxiLiteReadMasterType
axiReadSlave	out	AxiLiteReadSlaveType
axiWriteMaster	in	AxiLiteWriteMasterType
axiWriteSlave	out	AxiLiteWriteSlaveType
status	in	AxiAds42lb69StatusType
config	out	AxiAds42lb69ConfigType
adcClk	in	sl
adcRst	in	sl
axiClk	in	sl
axiRst	in	sl

---

The documentation for this design unit was generated from the following file:

• devices/Ti/ads42lb69/rtl/AxiAds42lb69Reg.vhd