AxiAds42lb69Pll.mapping Architecture Reference

Architecture >> AxiAds42lb69Pll::mapping

Constants
ADC_CLK_PERIOD_NS_C	real := 1 . 0E + 9 / ADC_CLK_FREQ_G

Signals
clkFeedBack	sl
clkFeedBackIn	sl
clkFeedBackOut	sl
sync	sl
syncOut	sl
adcInClk	sl

Instantiations
ibufgds_0	ibufgds
mmcme2_adv_0	mmcme2_adv
bufh_0	bufh
clkoutbufdiff_0	ClkOutBufDiff <Entity ClkOutBufDiff>
synchronizeroneshot_0	SynchronizerOneShot <Entity SynchronizerOneShot>
oddr_0	oddr
obufds_0	obufds
clkoutbufdiff_1	ClkOutBufDiff <Entity ClkOutBufDiff>
synchronizeroneshot_1	SynchronizerOneShot <Entity SynchronizerOneShot>
oddr_1	oddr
obufds_1	obufds
ibufgds_1	ibufgds
bufg_1	bufg
ibufgds_1	ibufgds
clkoutbufdiff_1	ClkOutBufDiff <Entity ClkOutBufDiff>
synchronizeroneshot_1	SynchronizerOneShot <Entity SynchronizerOneShot>
oddre1_1	oddre1
obufds_1	obufds
ibufgds_1	ibufgds
bufg_1	bufg
ibufgds_1	ibufgds

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The documentation for this design unit was generated from the following file:

• devices/Ti/ads42lb69/rtl/AxiAds42lb69Pll.vhd