AxiAds42lb69Pll Entity Reference

Inheritance diagram for AxiAds42lb69Pll:

Collaboration diagram for AxiAds42lb69Pll:

Entities
AxiAds42lb69Pll.mapping	architecture

Libraries
ieee
surf
unisim

Use Clauses
std_logic_1164
StdRtlPkg	Package <StdRtlPkg>
vcomponents

Generics
TPD_G	time := 1 ns
USE_PLL_G	boolean := true
USE_FBCLK_G	boolean := true
ADC_CLK_FREQ_G	real := 250 . 0E + 6
XIL_DEVICE_G	string := " 7SERIES "

Ports
adcClkP	out	sl
adcClkN	out	sl
adcSyncP	out	sl
adcSyncN	out	sl
adcClkFbP	in	sl
adcClkFbN	in	sl
adcSync	in	sl
adcClk	in	sl
adcRst	in	sl
adcClock	out	sl

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The documentation for this design unit was generated from the following file:

• devices/Ti/ads42lb69/rtl/AxiAds42lb69Pll.vhd