AxiAds42lb69Core Entity Reference

Inheritance diagram for AxiAds42lb69Core:

Collaboration diagram for AxiAds42lb69Core:

Entities
AxiAds42lb69Core.mapping	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_unsigned
std_logic_arith
StdRtlPkg	Package <StdRtlPkg>
AxiLitePkg	Package <AxiLitePkg>
AxiAds42lb69Pkg	Package <AxiAds42lb69Pkg>

Generics
TPD_G	time := 1 ns
SIM_SPEEDUP_G	boolean := false
USE_PLL_G	boolean := false
USE_FBCLK_G	boolean := true
ADC_CLK_FREQ_G	real := 250 . 00E + 6
DMODE_INIT_G	slv ( 1 downto 0 ) := " 00 "
DELAY_INIT_G	Slv9VectorArray ( 1 downto 0 , 7 downto 0 ) := ( others = > ( others = > ( others = > ' 0 ' ) ) )
IODELAY_GROUP_G	string := " AXI_ADS42LB69_IODELAY_GRP "
XIL_DEVICE_G	string := " 7SERIES "

Ports
adcIn	in	AxiAds42lb69InType
adcOut	out	AxiAds42lb69OutType
adcSync	in	sl
adcData	out	Slv16Array ( 1 downto 0 )
axiReadMaster	in	AxiLiteReadMasterType
axiReadSlave	out	AxiLiteReadSlaveType
axiWriteMaster	in	AxiLiteWriteMasterType
axiWriteSlave	out	AxiLiteWriteSlaveType
axiClk	in	sl
axiRst	in	sl
adcClk	in	sl
adcRst	in	sl
refClk200MHz	in	sl
refRst200MHz	in	sl := ' 0 '

---

The documentation for this design unit was generated from the following file:

• devices/Ti/ads42lb69/rtl/AxiAds42lb69Core.vhd