Architecture >> AxiAd5780Reg::rtl

Processes
comb	( axiReadMaster , axiRst , axiWriteMaster , dacRefreshRate , r , regIn )
seq	( axiClk )

Constants
DOUBLE_SCK_FREQ_C	*real := SPI_CLK_FREQ_G 2 . 0E + 0**
HALF_SCK_PERIOD_C	natural := ( getTimeRatio ( AXI_CLK_FREQ_G , DOUBLE_SCK_FREQ_C ) ) - 1
HALF_SCK_PERIOD_INIT_C	slv ( 31 downto 0 ) := toSlv ( HALF_SCK_PERIOD_C , 32 )
REG_INIT_C	RegType := ( ' 1 ' , AXI_AD5780_CONFIG_INIT_C , AXI_LITE_READ_SLAVE_INIT_C , AXI_LITE_WRITE_SLAVE_INIT_C )

Signals
r	RegType := REG_INIT_C
rin	RegType
regIn	AxiAd5780StatusType := AXI_AD5780_STATUS_INIT_C
regOut	AxiAd5780ConfigType := AXI_AD5780_CONFIG_INIT_C
dacRefreshRate	slv ( STATUS_CNT_WIDTH_G- 1 downto 0 )

Records
RegType

Instantiations
synctrigrate_inst	SyncTrigRate <Entity SyncTrigRate>

The documentation for this design unit was generated from the following file:

Processes

Constants