AxiAd5780Reg Entity Reference

Inheritance diagram for AxiAd5780Reg:

Collaboration diagram for AxiAd5780Reg:

Entities
AxiAd5780Reg.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_unsigned
std_logic_arith
StdRtlPkg	Package <StdRtlPkg>
AxiLitePkg	Package <AxiLitePkg>
AxiAd5780Pkg	Package <AxiAd5780Pkg>

Generics
TPD_G	time := 1 ns
STATUS_CNT_WIDTH_G	natural range 1 to 32 := 32
AXI_CLK_FREQ_G	real := 200 . 0E + 6
SPI_CLK_FREQ_G	real := 25 . 0E + 6

Ports
axiReadMaster	in	AxiLiteReadMasterType
axiReadSlave	out	AxiLiteReadSlaveType
axiWriteMaster	in	AxiLiteWriteMasterType
axiWriteSlave	out	AxiLiteWriteSlaveType
status	in	AxiAd5780StatusType
config	out	AxiAd5780ConfigType
axiClk	in	sl
axiRst	in	sl
dacRst	out	sl

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The documentation for this design unit was generated from the following file:

• devices/AnalogDevices/ad5780/rtl/AxiAd5780Reg.vhd