AxiAd5780Core.rtl Architecture Reference

Architecture >> AxiAd5780Core::rtl

Processes
PROCESS_190	( axiClk )

Signals
status	AxiAd5780StatusType
config	AxiAd5780ConfigType
dacRst	sl
dacDataMux	slv ( 17 downto 0 )

Instantiations
axiad5780reg_inst	AxiAd5780Reg <Entity AxiAd5780Reg>
axiad5780ser_inst	AxiAd5780Ser <Entity AxiAd5780Ser>

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The documentation for this design unit was generated from the following file:

• devices/AnalogDevices/ad5780/rtl/AxiAd5780Core.vhd