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AxiAd5780Ser Entity Reference
Inheritance diagram for AxiAd5780Ser:Entities | |
| AxiAd5780Ser.rtl | architecture |
Libraries | |
| ieee | |
| surf | |
Use Clauses | |
| std_logic_1164 | |
| std_logic_unsigned | |
| std_logic_arith | |
| StdRtlPkg | Package <StdRtlPkg> |
| AxiAd5780Pkg | Package <AxiAd5780Pkg> |
Generics | |
| TPD_G | time := 1 ns |
| AXI_CLK_FREQ_G | real := 200 . 0E + 6 |
Ports | ||
| dacIn | in | AxiAd5780InType |
| dacOut | out | AxiAd5780OutType |
| halfSckPeriod | in | slv ( 31 downto 0 ) |
| sdoDisable | in | sl |
| binaryOffset | in | sl |
| dacTriState | in | sl |
| opGnd | in | sl |
| rbuf | in | sl |
| dacData | in | slv ( 17 downto 0 ) |
| dacUpdated | out | sl |
| axiClk | in | sl |
| axiRst | in | sl |
| dacRst | in | sl |
The documentation for this design unit was generated from the following file:
- devices/AnalogDevices/ad5780/rtl/AxiAd5780Ser.vhd
