AxiAd5780Ser.rtl Architecture Reference

Architecture >> AxiAd5780Ser::rtl

Processes
comb	( binaryOffset , dacData , dacRst , dacTriState , halfSckPeriod , opGnd , r , rbuf , sdoDisable )
seq	( axiClk )

Constants
CS_WAIT_C	natural := ( getTimeRatio ( AXI_CLK_FREQ_G , 20 . 0E + 6 ) )
REG_INIT_C	RegType := ( ' 0 ' , ' 1 ' , ' 1 ' , ' 1 ' , ' 0 ' , ( others = > ' 0 ' ) , ( others = > ' 0 ' ) , 0 , ( others = > ' 0 ' ) , RST_S )

Types
StateType	( RST_S , RST_WAIT_S , SCK_HIGH_S , SCK_LOW_S , CS_HI_S )

Signals
r	RegType := REG_INIT_C
rin	RegType

Records
RegType

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The documentation for this design unit was generated from the following file:

• devices/AnalogDevices/ad5780/rtl/AxiAd5780Ser.vhd