Ad9681Config.rtl Architecture Reference

Architecture >> Ad9681Config::rtl

Processes
comb	( axilReadMaster , axilRst , axilWriteMaster , r , rdData , rdEn )
seq	( axilClk )

Constants
CHIP_SEL_WIDTH_C	integer := log2 ( NUM_CHIPS_G )
PWDN_ADDR_BIT_C	integer := 11 + CHIP_SEL_WIDTH_C
PWDN_ADDR_C	slv ( PWDN_ADDR_BIT_C downto 0 ) := toSlv ( 2 ** PWDN_ADDR_BIT_C , PWDN_ADDR_BIT_C+ 1 )
REG_INIT_C	RegType := ( state = > WAIT_AXI_TXN_S , axilReadSlave = > AXI_LITE_READ_SLAVE_INIT_C , axilWriteSlave = > AXI_LITE_WRITE_SLAVE_INIT_C , chipSel = > ( others = > ' 0 ' ) , wrData = > ( others = > ' 0 ' ) , wrEn = > ' 0 ' , pdwn = > ( others = > ' 0 ' ) )

Types
StateType	( WAIT_AXI_TXN_S , WAIT_CYCLE_S , WAIT_SPI_TXN_DONE_S )

Signals
rdData	slv ( 23 downto 0 )
rdEn	sl
coreSclk	sl
coreSDin	sl
coreSDout	sl
coreCsb	slv ( NUM_CHIPS_G- 1 downto 0 )
sdioDir	sl
shiftCount	slv ( bitSize ( 24 ) - 1 downto 0 )
r	RegType := REG_INIT_C
rin	RegType

Records
RegType

Instantiations
spimaster_1	SpiMaster <Entity SpiMaster>
sdio_iobuft	IoBufWrapper <Entity IoBufWrapper>

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The documentation for this design unit was generated from the following file:

• devices/AnalogDevices/ad9681/core/Ad9681Config.vhd