Ad9681Config Entity Reference

Inheritance diagram for Ad9681Config:

Collaboration diagram for Ad9681Config:

Entities
Ad9681Config.rtl	architecture

Libraries
ieee
surf
unisim

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned
StdRtlPkg	Package <StdRtlPkg>
AxiLitePkg	Package <AxiLitePkg>
vcomponents

Generics
TPD_G	time := 1 ns
NUM_CHIPS_G	positive := 1
SCLK_PERIOD_G	real := 1 . 0E - 6
AXIL_CLK_PERIOD_G	real := 8 . 0E - 9

Ports
axilClk	in	sl
axilRst	in	sl
axilReadMaster	in	AxiLiteReadMasterType
axilReadSlave	out	AxiLiteReadSlaveType
axilWriteMaster	in	AxiLiteWriteMasterType
axilWriteSlave	out	AxiLiteWriteSlaveType
adcPdwn	out	slv ( NUM_CHIPS_G- 1 downto 0 )
adcSclk	out	sl
adcSdio	inout	sl
adcCsb	out	slv ( NUM_CHIPS_G- 1 downto 0 )

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The documentation for this design unit was generated from the following file:

• devices/AnalogDevices/ad9681/core/Ad9681Config.vhd