SURF  1.0
SaltUltraScale.vhd
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1 -------------------------------------------------------------------------------
2 -- File : SaltUltraScale.vhd
3 -- Company : SLAC National Accelerator Laboratory
4 -- Created : 2015-06-15
5 -- Last update: 2017-02-10
6 -------------------------------------------------------------------------------
7 -- Description: SLAC Asynchronous Logic Transceiver (SALT) UltraScale Core
8 -------------------------------------------------------------------------------
9 -- This file is part of 'SLAC Firmware Standard Library'.
10 -- It is subject to the license terms in the LICENSE.txt file found in the
11 -- top-level directory of this distribution and at:
12 -- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html.
13 -- No part of 'SLAC Firmware Standard Library', including this file,
14 -- may be copied, modified, propagated, or distributed except according to
15 -- the terms contained in the LICENSE.txt file.
16 -------------------------------------------------------------------------------
17 
18 library ieee;
19 use ieee.std_logic_1164.all;
20 
21 use work.StdRtlPkg.all;
22 use work.AxiStreamPkg.all;
23 use work.SsiPkg.all;
24 
25 library unisim;
26 use unisim.vcomponents.all;
27 
28 --! @see entity
29  --! @ingroup protocols_salt_xilinxUltraScale
30 entity SaltUltraScale is
31  generic (
32  TPD_G : time := 1 ns;
33  TX_ENABLE_G : boolean := true;
34  RX_ENABLE_G : boolean := true;
35  COMMON_TX_CLK_G : boolean := false; -- Set to true if sAxisClk and clk are the same clock
36  COMMON_RX_CLK_G : boolean := false; -- Set to true if mAxisClk and clk are the same clock
37  SLAVE_AXI_CONFIG_G : AxiStreamConfigType := ssiAxiStreamConfig(4);
38  MASTER_AXI_CONFIG_G : AxiStreamConfigType := ssiAxiStreamConfig(4));
39  port (
40  -- TX Serial Stream
41  txP : out sl;
42  txN : out sl;
43  -- RX Serial Stream
44  rxP : in sl;
45  rxN : in sl;
46  -- Reference Signals
47  clk125MHz : in sl;
48  rst125MHz : in sl;
49  clk312MHz : in sl;
50  clk625MHz : in sl;
51  iDelayCtrlRdy : in sl;
52  mmcmLocked : in sl := '1';
53  loopback : in sl := '0';
54  powerDown : in sl := '0';
55  linkUp : out sl;
56  -- Slave Port
57  sAxisClk : in sl;
58  sAxisRst : in sl;
59  sAxisMaster : in AxiStreamMasterType;
60  sAxisSlave : out AxiStreamSlaveType;
61  -- Master Port
62  mAxisClk : in sl;
63  mAxisRst : in sl;
64  mAxisMaster : out AxiStreamMasterType;
65  mAxisSlave : in AxiStreamSlaveType);
66 end SaltUltraScale;
67 
68 architecture mapping of SaltUltraScale is
69 
70  component SaltUltraScaleCore
71  port (
72  -----------------------------
73  -- LVDS transceiver Interface
74  -----------------------------
75  txp : out std_logic; -- Differential +ve of serial transmission from PMA to PMD.
76  txn : out std_logic; -- Differential -ve of serial transmission from PMA to PMD.
77  rxp : in std_logic; -- Differential +ve for serial reception from PMD to PMA.
78  rxn : in std_logic; -- Differential -ve for serial reception from PMD to PMA.
79  clk125m : in std_logic;
80  mmcm_locked : in std_logic;
81  sgmii_clk_r : out std_logic; -- Clock for client MAC (125Mhz, 12.5MHz or 1.25MHz).
82  sgmii_clk_f : out std_logic; -- Clock for client MAC (125Mhz, 12.5MHz or 1.25MHz).
83  sgmii_clk_en : out std_logic; -- Clock enable for client MAC
84  ----------------
85  -- Speed Control
86  ----------------
87  speed_is_10_100 : in std_logic; -- Core should operate at either 10Mbps or 100Mbps speeds
88  speed_is_100 : in std_logic; -- Core should operate at 100Mbps speed
89  clk625 : in std_logic;
90  clk312 : in std_logic;
91  idelay_rdy_in : in std_logic;
92  -----------------
93  -- GMII Interface
94  -----------------
95  gmii_txd : in std_logic_vector(7 downto 0); -- Transmit data from client MAC.
96  gmii_tx_en : in std_logic; -- Transmit control signal from client MAC.
97  gmii_tx_er : in std_logic; -- Transmit control signal from client MAC.
98  gmii_rxd : out std_logic_vector(7 downto 0); -- Received Data to client MAC.
99  gmii_rx_dv : out std_logic; -- Received control signal to client MAC.
100  gmii_rx_er : out std_logic; -- Received control signal to client MAC.
101  gmii_isolate : out std_logic; -- Tristate control to electrically isolate GMII.
102  ---------------
103  -- General IO's
104  ---------------
105  configuration_vector : in std_logic_vector(4 downto 0); -- Alternative to MDIO interface.
106  status_vector : out std_logic_vector(15 downto 0); -- Core status.
107  reset : in std_logic; -- Asynchronous reset for entire core.
108  signal_detect : in std_logic); -- Input from PMD to indicate presence of optical input.
109  end component;
110 
111  component SaltUltraScaleRxOnly
112  port (
113  -----------------------------
114  -- LVDS transceiver Interface
115  -----------------------------
116  rxp : in std_logic; -- Differential +ve for serial reception from PMD to PMA.
117  rxn : in std_logic; -- Differential -ve for serial reception from PMD to PMA.
118  clk125m : in std_logic;
119  mmcm_locked : in std_logic;
120  sgmii_clk_r : out std_logic; -- Clock for client MAC (125Mhz, 12.5MHz or 1.25MHz).
121  sgmii_clk_f : out std_logic; -- Clock for client MAC (125Mhz, 12.5MHz or 1.25MHz).
122  sgmii_clk_en : out std_logic; -- Clock enable for client MAC
123  ----------------
124  -- Speed Control
125  ----------------
126  speed_is_10_100 : in std_logic; -- Core should operate at either 10Mbps or 100Mbps speeds
127  speed_is_100 : in std_logic; -- Core should operate at 100Mbps speed
128  clk625 : in std_logic;
129  clk312 : in std_logic;
130  idelay_rdy_in : in std_logic;
131  -----------------
132  -- GMII Interface
133  -----------------
134  gmii_txd : in std_logic_vector(7 downto 0); -- Transmit data from client MAC.
135  gmii_tx_en : in std_logic; -- Transmit control signal from client MAC.
136  gmii_tx_er : in std_logic; -- Transmit control signal from client MAC.
137  gmii_rxd : out std_logic_vector(7 downto 0); -- Received Data to client MAC.
138  gmii_rx_dv : out std_logic; -- Received control signal to client MAC.
139  gmii_rx_er : out std_logic; -- Received control signal to client MAC.
140  gmii_isolate : out std_logic; -- Tristate control to electrically isolate GMII.
141  ---------------
142  -- General IO's
143  ---------------
144  configuration_vector : in std_logic_vector(4 downto 0); -- Alternative to MDIO interface.
145  status_vector : out std_logic_vector(15 downto 0); -- Core status.
146  reset : in std_logic; -- Asynchronous reset for entire core.
147  signal_detect : in std_logic); -- Input from PMD to indicate presence of optical input.
148  end component;
149 
150  component SaltUltraScaleTxOnly
151  port (
152  -----------------------------
153  -- LVDS transceiver Interface
154  -----------------------------
155  txp : out std_logic; -- Differential +ve of serial transmission from PMA to PMD.
156  txn : out std_logic; -- Differential -ve of serial transmission from PMA to PMD.
157  clk125m : in std_logic;
158  mmcm_locked : in std_logic;
159  sgmii_clk_r : out std_logic; -- Clock for client MAC (125Mhz, 12.5MHz or 1.25MHz).
160  sgmii_clk_f : out std_logic; -- Clock for client MAC (125Mhz, 12.5MHz or 1.25MHz).
161  sgmii_clk_en : out std_logic; -- Clock enable for client MAC
162  ----------------
163  -- Speed Control
164  ----------------
165  speed_is_10_100 : in std_logic; -- Core should operate at either 10Mbps or 100Mbps speeds
166  speed_is_100 : in std_logic; -- Core should operate at 100Mbps speed
167  clk625 : in std_logic;
168  clk312 : in std_logic;
169  -----------------
170  -- GMII Interface
171  -----------------
172  gmii_txd : in std_logic_vector(7 downto 0); -- Transmit data from client MAC.
173  gmii_tx_en : in std_logic; -- Transmit control signal from client MAC.
174  gmii_tx_er : in std_logic; -- Transmit control signal from client MAC.
175  gmii_rxd : out std_logic_vector(7 downto 0); -- Received Data to client MAC.
176  gmii_rx_dv : out std_logic; -- Received control signal to client MAC.
177  gmii_rx_er : out std_logic; -- Received control signal to client MAC.
178  gmii_isolate : out std_logic; -- Tristate control to electrically isolate GMII.
179  ---------------
180  -- General IO's
181  ---------------
182  configuration_vector : in std_logic_vector(4 downto 0); -- Alternative to MDIO interface.
183  status_vector : out std_logic_vector(15 downto 0); -- Core status.
184  reset : in std_logic; -- Asynchronous reset for entire core.
185  signal_detect : in std_logic); -- Input from PMD to indicate presence of optical input.
186  end component;
187 
188 
189  signal config : slv(4 downto 0);
190  signal status : slv(15 downto 0);
191 
192  signal txEn : sl;
193  signal txData : slv(7 downto 0);
194 
195  signal rxEn : sl;
196  signal rxErr : sl;
197  signal rxData : slv(7 downto 0);
198 
199 begin
200 
201  linkUp <= status(0);
202 
203  config(0) <= '1'; -- Unidirectional Enabled
204  config(1) <= loopback; -- loopback
205  config(2) <= powerDown; -- powerDown
206  config(3) <= '0'; -- Isolate Disabled
207  config(4) <= '0'; -- Auto-Negotiation Disabled
208 
209  FULL_DUPLEX : if (TX_ENABLE_G = true) and (RX_ENABLE_G = true) generate
210  U_SaltUltraScaleCore : SaltUltraScaleCore
211  port map(
212  -----------------------------
213  -- LVDS transceiver Interface
214  -----------------------------
215  txp => txP,
216  txn => txN,
217  rxp => rxP,
218  rxn => rxN,
219  clk125m => clk125MHz,
220  mmcm_locked => mmcmLocked,
221  sgmii_clk_r => open,
222  sgmii_clk_f => open,
223  sgmii_clk_en => open,
224  ----------------
225  -- Speed Control
226  ----------------
227  speed_is_10_100 => '0',
228  speed_is_100 => '0',
229  clk625 => clk625MHz,
230  clk312 => clk312MHz,
231  idelay_rdy_in => iDelayCtrlRdy,
232  -----------------
233  -- GMII Interface
234  -----------------
235  gmii_txd => txData,
236  gmii_tx_en => txEn,
237  gmii_tx_er => '0',
238  gmii_rxd => rxData,
239  gmii_rx_dv => rxEn,
240  gmii_rx_er => rxErr,
241  gmii_isolate => open,
242  ---------------
243  -- General IO's
244  ---------------
245  configuration_vector => config,
246  status_vector => status,
247  reset => rst125MHz,
248  signal_detect => '1');
249  end generate;
250 
251  RX_ONLY : if (TX_ENABLE_G = false) and (RX_ENABLE_G = true) generate
252  txp <= '0';
253  txn <= '1';
254  U_SaltUltraScaleCore : SaltUltraScaleRxOnly
255  port map(
256  -----------------------------
257  -- LVDS transceiver Interface
258  -----------------------------
259  rxp => rxP,
260  rxn => rxN,
261  clk125m => clk125MHz,
262  mmcm_locked => mmcmLocked,
263  sgmii_clk_r => open,
264  sgmii_clk_f => open,
265  sgmii_clk_en => open,
266  ----------------
267  -- Speed Control
268  ----------------
269  speed_is_10_100 => '0',
270  speed_is_100 => '0',
271  clk625 => clk625MHz,
272  clk312 => clk312MHz,
273  idelay_rdy_in => iDelayCtrlRdy,
274  -----------------
275  -- GMII Interface
276  -----------------
277  gmii_txd => x"00",
278  gmii_tx_en => '0',
279  gmii_tx_er => '0',
280  gmii_rxd => rxData,
281  gmii_rx_dv => rxEn,
282  gmii_rx_er => rxErr,
283  gmii_isolate => open,
284  ---------------
285  -- General IO's
286  ---------------
287  configuration_vector => config,
288  status_vector => status,
289  reset => rst125MHz,
290  signal_detect => '1');
291  end generate;
292 
293  TX_ONLY : if (TX_ENABLE_G = true) and (RX_ENABLE_G = false) generate
294  U_SaltUltraScaleCore : SaltUltraScaleTxOnly
295  port map(
296  -----------------------------
297  -- LVDS transceiver Interface
298  -----------------------------
299  txp => txP,
300  txn => txN,
301  clk125m => clk125MHz,
302  mmcm_locked => mmcmLocked,
303  sgmii_clk_r => open,
304  sgmii_clk_f => open,
305  sgmii_clk_en => open,
306  ----------------
307  -- Speed Control
308  ----------------
309  speed_is_10_100 => '0',
310  speed_is_100 => '0',
311  clk625 => clk625MHz,
312  clk312 => clk312MHz,
313  -----------------
314  -- GMII Interface
315  -----------------
316  gmii_txd => txData,
317  gmii_tx_en => txEn,
318  gmii_tx_er => '0',
319  gmii_rxd => open,
320  gmii_rx_dv => open,
321  gmii_rx_er => open,
322  gmii_isolate => open,
323  ---------------
324  -- General IO's
325  ---------------
326  configuration_vector => config,
327  status_vector => status,
328  reset => rst125MHz,
329  signal_detect => '1');
330  end generate;
331 
332  TX_ENABLE : if (TX_ENABLE_G = true) generate
333  SaltTx_Inst : entity work.SaltTx
334  generic map(
335  TPD_G => TPD_G,
336  SLAVE_AXI_CONFIG_G => SLAVE_AXI_CONFIG_G,
337  COMMON_TX_CLK_G => COMMON_TX_CLK_G)
338  port map(
339  -- Slave Port
340  sAxisClk => sAxisClk,
341  sAxisRst => sAxisRst,
342  sAxisMaster => sAxisMaster,
343  sAxisSlave => sAxisSlave,
344  -- GMII Interface
345  txEn => txEn,
346  txData => txData,
347  clk => clk125MHz,
348  rst => rst125MHz);
349  end generate;
350 
351  TX_DISABLE : if (TX_ENABLE_G = false) generate
352 
353  txData <= x"00";
354  txEn <= '0';
355  sAxisSlave <= AXI_STREAM_SLAVE_FORCE_C;
356 
357  end generate;
358 
359  RX_ENABLE : if (RX_ENABLE_G = true) generate
360  SaltRx_Inst : entity work.SaltRx
361  generic map(
362  TPD_G => TPD_G,
363  MASTER_AXI_CONFIG_G => MASTER_AXI_CONFIG_G,
364  COMMON_RX_CLK_G => COMMON_RX_CLK_G)
365  port map(
366  -- Master Port
367  mAxisClk => mAxisClk,
368  mAxisRst => mAxisRst,
369  mAxisMaster => mAxisMaster,
370  mAxisSlave => mAxisSlave,
371  -- GMII Interface
372  rxEn => rxEn,
373  rxErr => rxErr,
374  rxData => rxData,
375  clk => clk125MHz,
376  rst => rst125MHz);
377 
378  end generate;
379 
380  RX_DISABLE : if (RX_ENABLE_G = false) generate
381 
382  mAxisMaster <= AXI_STREAM_MASTER_INIT_C;
383 
384  end generate;
385 
386 end mapping;
SaltRx.mAxisSlave
in mAxisSlaveAxiStreamSlaveType
Definition: SaltRx.vhd:40
SaltTx.sAxisClk
in sAxisClksl
Definition: SaltTx.vhd:37
SaltRx.mAxisMaster
out mAxisMasterAxiStreamMasterType
Definition: SaltRx.vhd:39
SaltUltraScale.TPD_G
TPD_Gtime := 1 ns
Definition: SaltUltraScale.vhd:32
SaltUltraScale.MASTER_AXI_CONFIG_G
MASTER_AXI_CONFIG_GAxiStreamConfigType := ssiAxiStreamConfig( 4)
Definition: SaltUltraScale.vhd:38
SaltRx.rxEn
in rxEnsl
Definition: SaltRx.vhd:42
SaltUltraScale.COMMON_TX_CLK_G
COMMON_TX_CLK_Gboolean := false
Definition: SaltUltraScale.vhd:35
StdRtlPkg.sl
std_logic sl
Definition: StdRtlPkg.vhd:28
AxiStreamPkg.AXI_STREAM_MASTER_INIT_C
AxiStreamMasterType :=(tValid => '0',tData =>( others => '0'),tStrb =>( others => '1'),tKeep =>( others => '1'),tLast => '0',tDest =>( others => '0'),tId =>( others => '0'),tUser =>( others => '0')) AXI_STREAM_MASTER_INIT_C
Definition: AxiStreamPkg.vhd:40
SaltUltraScale.loopback
in loopbacksl := '0'
Definition: SaltUltraScale.vhd:53
SaltTx.SLAVE_AXI_CONFIG_G
SLAVE_AXI_CONFIG_GAxiStreamConfigType := ssiAxiStreamConfig( 4)
Definition: SaltTx.vhd:34
SaltUltraScale.mapping.txData
slv( 7 downto 0) txData
Definition: SaltUltraScale.vhd:193
SaltTx.sAxisMaster
in sAxisMasterAxiStreamMasterType
Definition: SaltTx.vhd:39
SaltUltraScale.mapping.status
slv( 15 downto 0) status
Definition: SaltUltraScale.vhd:190
SaltUltraScale.sAxisMaster
in sAxisMasterAxiStreamMasterType
Definition: SaltUltraScale.vhd:59
SaltTx.sAxisRst
in sAxisRstsl
Definition: SaltTx.vhd:38
SaltRx.rst
in rstsl
Definition: SaltRx.vhd:46
SaltRx.MASTER_AXI_CONFIG_G
MASTER_AXI_CONFIG_GAxiStreamConfigType := ssiAxiStreamConfig( 4)
Definition: SaltRx.vhd:34
SaltRx.clk
in clksl
Definition: SaltRx.vhd:45
SaltTx.sAxisSlave
out sAxisSlaveAxiStreamSlaveType
Definition: SaltTx.vhd:40
SaltUltraScale.powerDown
in powerDownsl := '0'
Definition: SaltUltraScale.vhd:54
SaltRx.rxErr
in rxErrsl
Definition: SaltRx.vhd:43
SaltTx.rst
in rstsl
Definition: SaltTx.vhd:45
SaltTx.clk
in clksl
Definition: SaltTx.vhd:44
SaltUltraScale.SLAVE_AXI_CONFIG_G
SLAVE_AXI_CONFIG_GAxiStreamConfigType := ssiAxiStreamConfig( 4)
Definition: SaltUltraScale.vhd:37
SaltTx.TPD_G
TPD_Gtime := 1 ns
Definition: SaltTx.vhd:32
SaltRx.mAxisRst
in mAxisRstsl
Definition: SaltRx.vhd:38
Salt7Series.ieee
_library_ ieeeieee
Definition: Salt7Series.vhd:18
SaltUltraScale.mapping.config
slv( 4 downto 0) config
Definition: SaltUltraScale.vhd:189
SaltRx.rxData
in rxDataslv( 7 downto 0)
Definition: SaltRx.vhd:44
SaltRx.TPD_G
TPD_Gtime := 1 ns
Definition: SaltRx.vhd:32
SaltUltraScale.sAxisSlave
out sAxisSlaveAxiStreamSlaveType
Definition: SaltUltraScale.vhd:60
SaltUltraScale.TX_ENABLE_G
TX_ENABLE_Gboolean := true
Definition: SaltUltraScale.vhd:33
SaltUltraScale.mAxisSlave
in mAxisSlaveAxiStreamSlaveType
Definition: SaltUltraScale.vhd:65
SaltTx.COMMON_TX_CLK_G
COMMON_TX_CLK_Gboolean := false
Definition: SaltTx.vhd:33
SaltRx.mAxisClk
in mAxisClksl
Definition: SaltRx.vhd:37
SaltUltraScale.RX_ENABLE_G
RX_ENABLE_Gboolean := true
Definition: SaltUltraScale.vhd:34
SaltRx.COMMON_RX_CLK_G
COMMON_RX_CLK_Gboolean := false
Definition: SaltRx.vhd:33
SaltUltraScale.mapping.rxData
slv( 7 downto 0) rxData
Definition: SaltUltraScale.vhd:197
AxiStreamPkg.AXI_STREAM_SLAVE_FORCE_C
AxiStreamSlaveType :=(tReady => '1') AXI_STREAM_SLAVE_FORCE_C
Definition: AxiStreamPkg.vhd:66
SaltTx.txData
out txDataslv( 7 downto 0)
Definition: SaltTx.vhd:43
SaltTx.txEn
out txEnsl
Definition: SaltTx.vhd:42
SaltUltraScale.mAxisMaster
out mAxisMasterAxiStreamMasterType
Definition: SaltUltraScale.vhd:64
SaltUltraScale.COMMON_RX_CLK_G
COMMON_RX_CLK_Gboolean := false
Definition: SaltUltraScale.vhd:36
SaltUltraScale.mmcmLocked
in mmcmLockedsl := '1'
Definition: SaltUltraScale.vhd:52
StdRtlPkg.slv
std_logic_vector slv
Definition: StdRtlPkg.vhd:29