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SaciMasterPkg.vhd
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-------------------------------------------------------------------------------
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-- File : SaciMasterPkg.vhd
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-- Company : SLAC National Accelerator Laboratory
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-- Created : 2012-08-14
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-- Last update: 2012-09-27
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-------------------------------------------------------------------------------
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-- Description: Saci Master Package File
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-------------------------------------------------------------------------------
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-- This file is part of 'SLAC Firmware Standard Library'.
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-- It is subject to the license terms in the LICENSE.txt file found in the
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-- top-level directory of this distribution and at:
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-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html.
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-- No part of 'SLAC Firmware Standard Library', including this file,
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-- may be copied, modified, propagated, or distributed except according to
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-- the terms contained in the LICENSE.txt file.
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-------------------------------------------------------------------------------
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library
IEEE
;
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use
IEEE
.std_logic_1164.
all
;
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use
ieee.numeric_std.
all
;
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use
work.
StdRtlPkg
.
all
;
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package
SaciMasterPkg
is
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--! @file
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--! @ingroup protocols_saci
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constant
SACI_WRITE_C
:
sl
:=
'
1
'
;
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constant
SACI_READ_C
:
sl
:=
'
0
'
;
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constant
SACI_NUM_SLAVES_C
:
positive
:=
4
;
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constant
SACI_CHIP_WIDTH_C
:
natural
:=
log2
(
SACI_NUM_SLAVES_C
)
;
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type
SaciMasterInType
is
record
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req
:
sl
;
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reset
:
sl
;
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chip
:
slv
(
SACI_CHIP_WIDTH_C
-
1
downto
0
)
;
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op
:
sl
;
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cmd
:
slv
(
6
downto
0
)
;
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addr
:
slv
(
11
downto
0
)
;
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wrData
:
slv
(
31
downto
0
)
;
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end
record
SaciMasterInType
;
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type
SaciMasterOutType
is
record
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ack
:
sl
;
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fail
:
sl
;
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rdData
:
slv
(
31
downto
0
)
;
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end
record
SaciMasterOutType
;
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constant
SACI_MASTER_IN_INIT_C
:
SaciMasterInType
:=
(
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req
=
>
'
0
'
,
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reset
=
>
'
0
'
,
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chip
=
>
(
others
=
>
'
0
'
)
,
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op
=
>
'
0
'
,
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cmd
=
>
(
others
=
>
'
0
'
)
,
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addr
=
>
(
others
=
>
'
0
'
)
,
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wrData
=
>
(
others
=
>
'
0
'
)
)
;
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constant
SACI_MASTER_OUT_INIT_C
:
SaciMasterOutType
:=
(
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ack
=
>
'
0
'
,
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fail
=
>
'
0
'
,
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rdData
=
>
(
others
=
>
'
0
'
)
)
;
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end
package
SaciMasterPkg
;
SaciMasterPkg.reset
sl reset
Definition:
SaciMasterPkg.vhd:34
SaciMasterPkg.SaciMasterInType
SaciMasterInType
Definition:
SaciMasterPkg.vhd:32
SaciMasterPkg.addr
slv( 11 downto 0) addr
Definition:
SaciMasterPkg.vhd:38
SaciMasterPkg.req
sl req
Definition:
SaciMasterPkg.vhd:33
StdRtlPkg.sl
std_logic sl
Definition:
StdRtlPkg.vhd:28
SaciMasterPkg.wrData
slv( 31 downto 0) wrData
Definition:
SaciMasterPkg.vhd:39
SaciMasterPkg.cmd
slv( 6 downto 0) cmd
Definition:
SaciMasterPkg.vhd:37
SaciMaster2.IEEE
_library_ IEEEIEEE
Definition:
SaciMaster2.vhd:18
SaciMasterPkg.SaciMasterOutType
SaciMasterOutType
Definition:
SaciMasterPkg.vhd:42
SaciMasterPkg.op
sl op
Definition:
SaciMasterPkg.vhd:36
SaciMasterPkg.ack
sl ack
Definition:
SaciMasterPkg.vhd:43
SaciMasterPkg.SACI_NUM_SLAVES_C
positive := 4 SACI_NUM_SLAVES_C
Definition:
SaciMasterPkg.vhd:29
SaciMasterPkg.SACI_WRITE_C
sl := '1' SACI_WRITE_C
Definition:
SaciMasterPkg.vhd:27
SaciMasterPkg.SACI_MASTER_OUT_INIT_C
SaciMasterOutType :=(ack => '0',fail => '0',rdData =>( others => '0')) SACI_MASTER_OUT_INIT_C
Definition:
SaciMasterPkg.vhd:57
SaciMasterPkg.SACI_READ_C
sl := '0' SACI_READ_C
Definition:
SaciMasterPkg.vhd:28
SaciMasterPkg.SACI_CHIP_WIDTH_C
natural := log2(SACI_NUM_SLAVES_C ) SACI_CHIP_WIDTH_C
Definition:
SaciMasterPkg.vhd:30
SaciMasterPkg.rdData
slv( 31 downto 0) rdData
Definition:
SaciMasterPkg.vhd:45
StdRtlPkg
Definition:
StdRtlPkg.vhd:23
SaciMasterPkg.SACI_MASTER_IN_INIT_C
SaciMasterInType :=(req => '0',reset => '0',chip =>( others => '0'),op => '0',cmd =>( others => '0'),addr =>( others => '0'),wrData =>( others => '0')) SACI_MASTER_IN_INIT_C
Definition:
SaciMasterPkg.vhd:48
SaciMasterPkg.fail
sl fail
Definition:
SaciMasterPkg.vhd:44
SaciMasterPkg.chip
slv( SACI_CHIP_WIDTH_C- 1 downto 0) chip
Definition:
SaciMasterPkg.vhd:35
StdRtlPkg.slv
std_logic_vector slv
Definition:
StdRtlPkg.vhd:29
SaciMasterPkg
Definition:
SaciMasterPkg.vhd:23
protocols
saci
rtl
SaciMasterPkg.vhd
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