SURF  1.0
SaciMasterPkg.vhd
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1 -------------------------------------------------------------------------------
2 -- File : SaciMasterPkg.vhd
3 -- Company : SLAC National Accelerator Laboratory
4 -- Created : 2012-08-14
5 -- Last update: 2012-09-27
6 -------------------------------------------------------------------------------
7 -- Description: Saci Master Package File
8 -------------------------------------------------------------------------------
9 -- This file is part of 'SLAC Firmware Standard Library'.
10 -- It is subject to the license terms in the LICENSE.txt file found in the
11 -- top-level directory of this distribution and at:
12 -- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html.
13 -- No part of 'SLAC Firmware Standard Library', including this file,
14 -- may be copied, modified, propagated, or distributed except according to
15 -- the terms contained in the LICENSE.txt file.
16 -------------------------------------------------------------------------------
17 
18 library IEEE;
19 use IEEE.std_logic_1164.all;
20 use ieee.numeric_std.all;
21 use work.StdRtlPkg.all;
22 
23 package SaciMasterPkg is
24 --! @file
25  --! @ingroup protocols_saci
26 
27  constant SACI_WRITE_C : sl := '1';
28  constant SACI_READ_C : sl := '0';
29  constant SACI_NUM_SLAVES_C : positive := 4;
30  constant SACI_CHIP_WIDTH_C : natural := log2(SACI_NUM_SLAVES_C);
31 
32  type SaciMasterInType is record
33  req : sl;
34  reset : sl;
35  chip : slv(SACI_CHIP_WIDTH_C-1 downto 0);
36  op : sl;
37  cmd : slv(6 downto 0);
38  addr : slv(11 downto 0);
39  wrData : slv(31 downto 0);
40  end record SaciMasterInType;
41 
42  type SaciMasterOutType is record
43  ack : sl;
44  fail : sl;
45  rdData : slv(31 downto 0);
46  end record SaciMasterOutType;
47 
49  req => '0',
50  reset => '0',
51  chip => (others => '0'),
52  op => '0',
53  cmd => (others => '0'),
54  addr => (others => '0'),
55  wrData => (others => '0'));
56 
58  ack => '0',
59  fail => '0',
60  rdData => (others => '0'));
61 
62 end package SaciMasterPkg;
slv( 11 downto 0) addr
std_logic sl
Definition: StdRtlPkg.vhd:28
slv( 31 downto 0) wrData
slv( 6 downto 0) cmd
_library_ IEEEIEEE
Definition: SaciMaster2.vhd:18
positive := 4 SACI_NUM_SLAVES_C
sl := '1' SACI_WRITE_C
SaciMasterOutType :=(ack => '0',fail => '0',rdData =>( others => '0')) SACI_MASTER_OUT_INIT_C
sl := '0' SACI_READ_C
natural := log2(SACI_NUM_SLAVES_C ) SACI_CHIP_WIDTH_C
slv( 31 downto 0) rdData
SaciMasterInType :=(req => '0',reset => '0',chip =>( others => '0'),op => '0',cmd =>( others => '0'),addr =>( others => '0'),wrData =>( others => '0')) SACI_MASTER_IN_INIT_C
slv( SACI_CHIP_WIDTH_C- 1 downto 0) chip
std_logic_vector slv
Definition: StdRtlPkg.vhd:29